True single phase clock dynamic CMOS circuit technique
1988 (English)In: IEEE International Symposium on Circuits and Systems, 1988, 1988, 475-478 p.Conference paper (Refereed)
Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3-μm CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew
Place, publisher, year, edition, pages
1988. 475-478 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-88618DOI: 10.1109/ISCAS.1988.14967OAI: oai:DiVA.org:liu-88618DiVA: diva2:605166
IEEE International Cymposium on Circuits and Systems, Espoo, Finland, 7-9 June 1988