A 200 MHz CMOS digital radio frequency memory chip with analog output
1993 (English)In: Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, 1993, 16.3.1-16.3.4 p.Conference paper (Refereed)
A single-chip architecture which realizes most of the intermediate-frequency (IF) part of a digital radio frequency memory (DRFM) is presented. The implementation in CMOS technology (Lnom = 1 μm), called the DRFMC, allows different modes of operation with 200-MHz clock frequency (400-MHz nominal). The modes are pulsed signal synthesis, delay line, or continuous-wave (CW) synthesis. The DRFMC is programmable via a DMA interface. A digital signal processing unit and a digital-to-analog converter have been included. The output is analog and digital, which supports cascading of several DRFMCs
Place, publisher, year, edition, pages
1993. 16.3.1-16.3.4 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-88622DOI: 10.1109/CICC.1993.590731ISBN: 0-7803-0826-3OAI: oai:DiVA.org:liu-88622DiVA: diva2:605171
IEEE 1993 Custom Integrated Circuits Conference (CICC '93), May 9-12 1993, San Diego, California