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Event driven data processing architecture applied to reconfigurable digital RF system
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
(English)Manuscript (preprint) (Other academic)
Abstract [en]

This paper describes a data processing architecture where events and time are in focus. This differs from traditional von Neumann and data flow architectures. Also function and performance are closely handled at all levels of description, implementation and execution. New instruction codes are defined and special circuitry is introduced to express and execute event and time operations. This results in reconfigurable software controlled functionality together with real-time performance close to a dedicated VLSI solution. The architecture is demonstrated in a real-time RF processing radar application and its theory, design, implementation, simulation and testing is presented. A prototype chip, complete with 32-kbyte signal memory, 2-kbyte instruction memory, four processing units in parallel and interfaces for digitized RF signals and host computer, is fabricated in 0.35 μm standard CMOS. Time events of signal data on two simultaneous 8 bit links can be controlled with a time resolution of one clock period. Measurements verified conect function and performance above 400 MHz clock frequency at 3.3 Volt supply. Power consumption is 3.6-Watt @320 MHz.

National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-88627OAI: diva2:605211
Available from: 2013-02-13 Created: 2013-02-13 Last updated: 2013-02-13
In thesis
1. CMOS circuits for digital RF systems
Open this publication in new window or tab >>CMOS circuits for digital RF systems
2002 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis describes some high performance CMOS circuits and architectures developed for digital signal processing of Radio Frequency (RF) signals. Experimental results are demonstrated in a generic radar jammer architecture.

The goal is to reach high performance RF system designs utilizing the continuous development of standard commercial CMOS processes. This is done using a comprehensive view with focus on three levels, circuits, devices and architectures. Finally these levels are joined in a system on chip (SoC).

At circuit level a new clocking strategy, the true single-phase-clock (TSPC) dynamic CMOS circuit technique, was introduced. TSPC is based on a single clock wire, which simplifies the clock distribution and give higher performance compared to earlier two and four wire solutions. Chips has been designed and fabricated to verify TSPC.

At device level two chips has been developed, fabricated and verified. First a single chip Digital Radio Frequency Memory (DRFM) with analog output containing digital parts and on chip D/A converter. Then a single chip Direct Digital Frequency Synthesizer (DDFS) with on chip D/A converters for four-phase analog output. Calculated sine and cosine values are based on ROM tables and interpolation. Both devices utilize TSPC to reach high performance and are frequently used in radar jammers, DRFM for storage of radar pulses and DDFS for frequency selection.

At architecture level the material covers three areas: Globally Updated Mesochronous Design Style (GUM-design-style), Expandable High Throughput Vector Based Access Memory Architecture, and Event Driven Data Processing Architecture.

GUM-design-style reduces the design effort needed in large high performance synchronous digital designs by early functional partitioning and identification of all needed high speed digital signal links between partitions in the system. Each function is then developed individually which reduces its complexity and by that its design effort needed. Global synchronism is obtained after integration by a calibration procedure.

Expandable High Throughput Vector Based Access Memory Architecture improves performance in terms of expandability and throughput for vector access compared to standard memories. Each memory chip has two high-speed data ports used only for connections to adjacent chip. One for connection upward, to device accessing information or a memory chip, the other for connection downward to another memory chip. Expandability is based on mentioned cascade coupling of chips and distributed control function. Memory content is accessed given start point and length of a vector, if the vector is stored on several chips then a distributed internal controller handle the internal management between the chips.

Finally, Event Driven Data Processing Architecture increases reconfigurable real-time system performance by extension of traditional programmable computing architecture, software and hardware, to express and execute event and time operations. The architecture is demonstrated in a real-time RF processing radar application.

All architectures have been used in chip design, and results verified by measurements.

Place, publisher, year, edition, pages
Linköping: Linköping studies in science and technology., 2002. 16 p.
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 775
National Category
Engineering and Technology
urn:nbn:se:liu:diva-34861 (URN)23738 (Local ID)91-7373-429-2 (ISBN)23738 (Archive number)23738 (OAI)
Public defence
2002-10-25, Sal Visionen, Linköpings Universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-02-13

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