Event driven data processing architecture applied to reconfigurable digital RF system
(English)Manuscript (preprint) (Other academic)
This paper describes a data processing architecture where events and time are in focus. This differs from traditional von Neumann and data flow architectures. Also function and performance are closely handled at all levels of description, implementation and execution. New instruction codes are defined and special circuitry is introduced to express and execute event and time operations. This results in reconfigurable software controlled functionality together with real-time performance close to a dedicated VLSI solution. The architecture is demonstrated in a real-time RF processing radar application and its theory, design, implementation, simulation and testing is presented. A prototype chip, complete with 32-kbyte signal memory, 2-kbyte instruction memory, four processing units in parallel and interfaces for digitized RF signals and host computer, is fabricated in 0.35 μm standard CMOS. Time events of signal data on two simultaneous 8 bit links can be controlled with a time resolution of one clock period. Measurements verified conect function and performance above 400 MHz clock frequency at 3.3 Volt supply. Power consumption is 3.6-Watt @320 MHz.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-88627OAI: oai:DiVA.org:liu-88627DiVA: diva2:605211