liu.seSearch for publications in DiVA
Change search
ReferencesLink to record
Permanent link

Direct link
Design and implementation of an approximate full adder and its use in FIR filters
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2013 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Implementation of the polyphase decomposed FIR filter structure involves two steps; the generation of the partial products and the efficient reduction of the generated partial products. The partial products are generated by a constant multiplication of the filter coefficients with the input data and the reduction of the partial products is done by building a pipelined adder tree using FAs and HAs. To improve the speed and to reduce the complexity of the reduction tree a4:2 counter is introduced into the reduction tree. The reduction tree is designed using a bit-level optimized ILP problem which has the objective function to minimize the overall cost of the hardware used. For this purpose the layout design for a 4:2 counter has been developed and the cost function has been derived by comparing the complexity of the design against a standard FA design.

The layout design for a 4:2 counter is implemented in a 65nm process using static CMOS logic style and DPL style. The average power consumption drawn from a 1V power supply, for the static CMOS design was found to be 16.8μWand for the DPL style it was 12.51μW. The worst case rise or fall time for the DPL logic was 350ps and for the static CMOS logic design it was found to be 260ps.

The usage of the 4:2 counter in the reduction tree infused errors into the filter response, but it helped to reduce the number of pipeline stages and also to improve the speed of the partial product reduction.

Place, publisher, year, edition, pages
2013. , 51 p.
Keyword [en]
FIR filters, bit-level optimization, 4:2 counter, static CMOS, DPL, 65nm process
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:liu:diva-89430ISRN: LiTH-ISY-EX--12/4565--SEOAI: diva2:607793
Subject / course
Electronics Systems
2012-05-28, Nöllstallet, Linköping Universitet, Linköping, 10:15 (English)
Available from: 2013-02-26 Created: 2013-02-25 Last updated: 2013-02-26Bibliographically approved

Open Access in DiVA

master thesis report(1551 kB)302 downloads
File information
File name FULLTEXT01.pdfFile size 1551 kBChecksum SHA-512
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Satheesh Varma, Nikhil
By organisation
Electronics SystemThe Institute of Technology
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 302 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Total: 140 hits
ReferencesLink to record
Permanent link

Direct link