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Compiling for VLIW DSPs
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology. (PELAB)ORCID iD: 0000-0001-5241-0026
2010 (English)In: Handbook of signal processing systems / [ed] Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala, New York: Springer, 2010, 1, 603-638 p.Chapter in book (Refereed)
Place, publisher, year, edition, pages
New York: Springer, 2010, 1. 603-638 p.
Keyword [en]
Compiler, code generation, digital signal processor, clustered VLIW architecture, instruction scheduling, instruction selection, register allocation, integrated code generation, VLIW DSP processors
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-91498ISBN: 9781441963444 (print)ISBN: 9781441963451 (print)OAI: oai:DiVA.org:liu-91498DiVA: diva2:618126
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Integrated Software Pipelining
Available from: 2013-04-25 Created: 2013-04-25 Last updated: 2015-03-23Bibliographically approved

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SpringerLinkFind book at a Swedish library/Hitta boken i ett svenskt bibliotekFind book in another country/Hitta boken i ett annat land

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Kessler, Christoph

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Total: 57 hits
CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf