Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs
2012 (English)In: 22nd International Conference on Field Programmable Logic and Applications (FPL) / [ed] Dirk Koch, Satnam Singh, Jim Torresen, Piscataway, NJ, USA: IEEE Communications Society, 2012, 71-74 p.Conference paper (Refereed)
Many contemporary FPGAs have introduced a pre-adder before the hard multipliers, primarily aimed at linear-phase FIR filters. In this work, structural modifications are proposed with the aim of reducing the LUT resource utilization and, finally, using the pre-adder for implementing single path delay feedback pipeline FFTs. The results show that two thirds of the LUT resources can be saved when the pre-adder has bypass functionality, as in the Xilinx 6 and 7 series, compared to a direct mapping.
Place, publisher, year, edition, pages
Piscataway, NJ, USA: IEEE Communications Society, 2012. 71-74 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-91690DOI: 10.1109/FPL.2012.6339243ISBN: 978-1-4673-2256-0 (Print)ISBN: 978-1-4673-2255-3 (e-ISBN)OAI: oai:DiVA.org:liu-91690DiVA: diva2:618605
22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway, 29-31 August 2012