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A PRET microarchitecture implementation with repeatable timing and competitive performance
University of California, Berkeley, USA.
Saarland University, Saarbrücken, Germany.
Linköping University, Department of Computer and Information Science, PELAB - Programming Environment Laboratory. Linköping University, The Institute of Technology.
University of California, Berkeley, USA.
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2012 (English)In: Computer Design (ICCD), 2012, IEEE , 2012, 87-93 p.Conference paper (Refereed)
Abstract [en]

We contend that repeatability of execution times is crucial to the validity of testing of real-time systems. However, computer architecture designs fail to deliver repeatable timing, a consequence of aggressive techniques that improve average-case performance. This paper introduces the Precision-Timed ARM (PTARM), a precision-timed (PRET) microarchitecture implementation that exhibits repeatable execution times without sacrificing performance. The PTARM employs a repeatable thread-interleaved pipeline with an exposed memory hierarchy, including a repeatable DRAM controller. Our benchmarks show an improved throughput compared to a single-threaded in-order five-stage pipeline, given sufficient parallelism in the software.

Place, publisher, year, edition, pages
IEEE , 2012. 87-93 p.
, IEEE International Conference on Computer Design, ISSN 1063-6404
National Category
Computer Science
URN: urn:nbn:se:liu:diva-93303DOI: 10.1109/ICCD.2012.6378622ISBN: 978-1-4673-3051-0OAI: diva2:624064
IEEE 30th International Conference on Computer Design(ICCD 2012), 30 september - 3 October 2012, Montreal, QC, Canada
Available from: 2013-05-30 Created: 2013-05-30 Last updated: 2013-08-27Bibliographically approved

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Broman, David
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PELAB - Programming Environment LaboratoryThe Institute of Technology
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