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Efficient On-Chip Pipelined Streaming Computations on Scalable Manycore Architectures
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology. (PELAB)ORCID iD: 0000-0002-1940-3331
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.ORCID iD: 0000-0001-5241-0026
Fern Universitat in Hagen, Fac. of Math. and Computer Science, Hagen, Germany.
2012 (English)Conference paper, Poster (with or without abstract) (Other academic)
Abstract [en]

Performance of manycore processors is limited by programs' use of off-chip main memory. Streaming computation organized in a pipeline limits accesses to main memory to tasks at boundaries of the pipeline to read or write to main memory. The Single Chip Cloud computer (SCC) offers 48 cores linked by a high-speed on-chip network, and allows the implementation of such on-chip pipelined technique. We assess the performance and constraints provided by the SCC and investigate on on-chip pipelined mergesort as a case study for streaming computations. We found that our on-chip pipelined mergesort yields significant speedup over classic parallel mergesort on SCC. The technique should bring improvement in power consumption and should be portable to other manycore, network-on-chip architectures such as Tilera's processors.

Place, publisher, year, edition, pages
Ghent: HiPEAC , 2012. , 4 p.
Keyword [en]
high-performance scc mapping parallel multicore manycore energy mergesort memory-intensive benchmark mpi communication pipeline cache scalability
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:liu:diva-93421ISBN: 978-90-3821-987-5 (print)OAI: oai:DiVA.org:liu-93421DiVA: diva2:624511
Conference
Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 8-14 july, Fiuggi, Italy
Projects
high-performance scc mapping parallel multicore manycore energy mergesort memory-intensive benchmark mpi communication pipeline cache scalable
Available from: 2013-05-31 Created: 2013-05-31 Last updated: 2014-10-08Bibliographically approved

Open Access in DiVA

Efficient On-Chip Pipelined Streaming Computations on Scalable Manycore Architectures(266 kB)255 downloads
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Type fulltextMimetype application/pdf

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http://www.hipeac.net/acaces2012/

Authority records BETA

Melot, NicolasKessler, Christoph

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf