Efficient On-Chip Pipelined Streaming Computations on Scalable Manycore Architectures
2012 (English)Conference paper, Poster (Other academic)
Performance of manycore processors is limited by programs' use of off-chip main memory. Streaming computation organized in a pipeline limits accesses to main memory to tasks at boundaries of the pipeline to read or write to main memory. The Single Chip Cloud computer (SCC) offers 48 cores linked by a high-speed on-chip network, and allows the implementation of such on-chip pipelined technique. We assess the performance and constraints provided by the SCC and investigate on on-chip pipelined mergesort as a case study for streaming computations. We found that our on-chip pipelined mergesort yields significant speedup over classic parallel mergesort on SCC. The technique should bring improvement in power consumption and should be portable to other manycore, network-on-chip architectures such as Tilera's processors.
Place, publisher, year, edition, pages
Ghent: HiPEAC , 2012. , 4 p.
high-performance scc mapping parallel multicore manycore energy mergesort memory-intensive benchmark mpi communication pipeline cache scalability
IdentifiersURN: urn:nbn:se:liu:diva-93421ISBN: 978-90-3821-987-5OAI: oai:DiVA.org:liu-93421DiVA: diva2:624511
Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 8-14 july, Fiuggi, Italy
Projectshigh-performance scc mapping parallel multicore manycore energy mergesort memory-intensive benchmark mpi communication pipeline cache scalable