The aim of this thesis is twofold. Investigating and presenting information on how the EtherCAT fieldbus protocol performs theoretically in a smaller network and to present an implementation of the protocol on a FPGA based device and use it as a base to test and confirm that the theoretical numbers are correct in practice.

The focus is put toward a small network of up to 16 nodes which continuously produce data which must be moved to a single master node. Focus is not solely put on the network transactions but also includes the transactions performed on the producing devices to make the data available to the EtherCAT network. These devices use a licensed IP core which provide the media access.

Through calculations based on available information on how the involved parts work, the theoretical study shows that with each node producing 32 bytes worth of data, the achievable delay when starting the transaction from the master until all data is received back is below 80 μs. The throughput of useful data is up toward 90% of the 100 Mbit/s line in many of the considered cases. The network delay added in nodes is in the order of 1.5 μs. In terms of intra-node delay, it is shown that the available interfaces, which move data into the EtherCAT part of the device, are capable of handling the necessary speeds to not reduce performance overall.

An implementation of a device is presented; it is written in VHDL and implemented on a Xilinx FPGA. It is verified through simulation to perform within the expected bounds calculated in the theoretical study. An analysis of the resource usage is also presented.