An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
2013 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, Vol. 60, no 7, 387-391 p.Article in journal (Refereed) Published
This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2013. Vol. 60, no 7, 387-391 p.
Digital Delta Sigma modulator (DDSM), digital-to-analog converter (DAC), MASH, oversampling, time interleaving
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-96713DOI: 10.1109/TCSII.2013.2258272ISI: 000322030600004OAI: oai:DiVA.org:liu-96713DiVA: diva2:642968
Funding Agencies|Swedish Foundation for Strategic Research (SSF)||2013-08-232013-08-232015-08-19