A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage
2013 (English)Conference paper (Refereed)
A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator's noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.
Place, publisher, year, edition, pages
IEEE , 2013. 1-6 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-97265DOI: 10.1109/VLSI-SoC.2013.6673235ISI: 000332046100001OAI: oai:DiVA.org:liu-97265DiVA: diva2:645843
IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 7-9 October, Istanbul, Turkey