Extensible Recognition of Algorithmic Patterns in DSP Programs for Automatic Parallelization
2013 (English)In: International journal of parallel programming, ISSN 0885-7458, E-ISSN 1573-7640, Vol. 41, no 6, 806-824 p.Article in journal (Refereed) Published
We introduce an extensible knowledge based tool for idiom (pattern) recognition in DSP (digital signal processing) programs. Our tool utilizes functionality provided by the Cetus compiler infrastructure for detecting certain computation patterns that frequently occur in DSP code. We focus on recognizing patterns for for-loops and statements in their bodies as these often are the performance critical constructs in DSP applications for which replacement by highly optimized, target-specific parallel algorithms will be most profitable. For better structuring and efficiency of pattern recognition, we classify patterns by different levels of complexity such that patterns in higher levels are defined in terms of lower level patterns. The tool works statically on the intermediate representation. For better extensibility and abstraction, most of the structural part of recognition rules is specified in XML form to separate the tool implementation from the pattern specifications. Information about detected patterns will later be used for optimized code generation by local algorithm replacement e.g. for the low-power high-throughput multicore DSP architecture ePUMA.
Place, publisher, year, edition, pages
Springer Verlag (Germany) , 2013. Vol. 41, no 6, 806-824 p.
Automatic parallelization, Algorithmic pattern recognition, Cetus, DSP, DSP code parallelization, Compiler frameworks
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-97429DOI: 10.1007/s10766-012-0229-2ISI: 000322726300005OAI: oai:DiVA.org:liu-97429DiVA: diva2:647901