Implementation of a Low-Cost Analog-to-Digital Converter for Audio Applications Using an FPGA
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
The aim of this master’s thesis is to implement an ADC (Analog-to-Digital Converter) foraudio applications using external components together with an FPGA (Field-ProgrammableGate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bitresolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually someunused pins and logic available in the FPGA that can be used for other purposes. This istaken advantage of, to make the ADC as low-cost as possible.This thesis presents two solutions: (1) a - (Sigma-Delta) converter with a ﬁrst order passive loop-ﬁlter and (2) a - converter with a second order active loop-ﬁlter. The solutionshave been designed on a PCB (Printed Curcuit Board) with a Xilinx Spartan-6 FPGA. Bothsolutions take advantage of the LVDS (Low-Voltage-Diﬀerential-Signaling) input buﬀers inthe FPGA.(1) achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Eﬀectivenumber of bits) 10.06 bits) and (2) achieves a peak SNDR of 80.3 dB (ENOB 13.04). (1) isvery low-cost ($0.06) but is not suitable for high-precision audio applications. (2) costs $0.53for mono audio and $0.71 for stereo audio and is comparable with the solution used today:an external ADC (PCM1807).
Place, publisher, year, edition, pages
2013. , 68 p.
ADC, Sigma-Delta, FPGA, LVDS
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-96009ISRN: LiTH-ISY-EX--13/4711--SEOAI: oai:DiVA.org:liu-96009DiVA: diva2:650302
Subject / course