A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS
2013 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, 69-78 p.Article in journal (Refereed) Published
This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.
Place, publisher, year, edition, pages
Springer, 2013. Vol. 77, no 1, 69-78 p.
Analog-to-digital converter (ADC), Delta-sigma modulator, Operational transconductance amplifier (OTA), Medical implant device Load-compensated two-stage amplifier
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-100027DOI: 10.1007/s10470-013-0087-xISI: 000324828000007OAI: oai:DiVA.org:liu-100027DiVA: diva2:659442
The 30th NORCHIP conference, November 12, Copenhagen, Denmark