Reconfigurable FSM for Ultra-Low Power Wireless Sensor Network Nodes
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour.In order to achieve flexibility in node functionality, it is common to adopt reconfigurablearchitecture for WSN nodes. FPGA-based architectures are popular reconfigurable architectures bywhich WSN nodes can be programmed to take up different roles across time. Area and power are themajor overheads in FPGA based architectures, where interconnect consumes more power and area thanlogic cells. The contemporary WSN standard requires longer battery life and micro size nodes for easyplacement and maintenance-free operation for years together.Three solutions have been studied and evaluated to approach this problem: 1) Homogenousembedded FPGA platform, 2) Power gated reconfigurable finite state machines and 3) Pass transistorlogic (PTL) based reconfigurable finite state machines. Embedded FPGA is a CMOS 65nm customdeveloped small homogenous FPGA which holds the functionality of the WSN nodes and it will bedynamically reconfigured from time to time to change the functionality of the node. In Power gatedreconfigurable FSM architecture, the functionality of the node is expressed in the form of finite statemachines, which will be implemented in a LUT based power gated design. In PTL based reconfigurablefinite state machine architecture, the finite state machines are completely realized using PTL basedcustom designed sets of library components. Low power configuration memory is used to dynamicallyreconfigure the design with various FSMs at different times.
Place, publisher, year, edition, pages
2013. , 78 p.
Wireless Sensor Networks (WSN), Low Power, Pass Transistor Logic (PTL), FPGA, FSM, Reconfiguration
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-100121ISRN: LiTH-ISY-EX--13/4724--SEOAI: oai:DiVA.org:liu-100121DiVA: diva2:659819
Subject / course
2013-10-16, Filtret, 10:00 (English)
Alvandpour, Atila, Professor