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Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2012 (English)In: Digital System Design (DSD), 2012, IEEE , 2012, 529-532 p.Conference paper, Published paper (Refereed)
Abstract [en]

Single Instruction Multiple Data (SIMD) architecture has been proved to be a suitable parallel processor architecture for media and communication signal processing. But the computing overhead such as memory access latency and vector data permutation limit the performance of conventional SIMD processor. Solutions such as combined VLIW and SIMD architecture are designed with an increased complexity for compiler design and assembly programming. This paper introduces the SIMD processor in the ePUMA1 platform which uses deep execution pipeline and flexible parallel memory to achieve high computing performance. Its deep pipeline can execute combined operations in one cycle. And the parallel memory architecture supports conflict free parallel data access. It solves the problem of large vector permutation in a short vector SIMD machine in a more efficient way than conventional vector permutation instruction. We evaluate the architecture by implementing the soft decision Viterbi algorithm for convolutional decoding. The result is compared with other architectures, including TI C54x, CEVA TeakLike III, and PowerPC AltiVec, to show ePUMA’s computing efficiency advantage.

Place, publisher, year, edition, pages
IEEE , 2012. 529-532 p.
Keyword [en]
convolutional codes;decoding;parallel processing;random-access storage;CEVA TeakLike III;PowerPC AltiVec;TI C54x;VLIW architecture;assembly programming;communication signal processing;compiler design;conflict free parallel data access;convolutional decoding;deep-pipelined SIMD processor;ePUMA1 platform;flexible parallel memory;media signal processing;memory access latency;parallel processor architecture;pipeline parallel memory;short vector SIMD machine;single instruction multiple data architecture;soft decision Viterbi algorithm;vector data permutation limit;vector permutation instruction;Computer architecture;Convolution;Convolutional codes;Decoding;Measurement;Vectors;Viterbi algorithm;Convolutional decoding;Parallel memory;SIMD;Viterbi;ePUMA
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-100380DOI: 10.1109/DSD.2012.34ISBN: 978-1-4673-2498-4 (print)OAI: oai:DiVA.org:liu-100380DiVA: diva2:661711
Conference
15th Euromicro Conference on Digital System Design (DSD 2012), 5-8 September 2012, Izmir, Turkey
Projects
ePUMA
Available from: 2013-11-04 Created: 2013-11-04 Last updated: 2013-11-18Bibliographically approved

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Wang, JianKarlsson, AndréasSohl, JoarLiu, Dake

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