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An Efficient Streaming Star Network for Multi-core Parallel DSP Processor
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2011 (English)In: Networking and Computing (ICNC), 2011, IEEE , 2011, 332-336 p.Conference paper, Published paper (Refereed)
Abstract [en]

As more and more computing components are integrated into one digital signal processing (DSP) system to achieve high computing power by executing tasks in parallel, it is soon observed that the inter-processor and processor to memory communication overheads become the performance bottleneck and limit the scalability of a multi-processor platform. For chip multiprocessor (CMP) DSP systems targeting on predictable computing, an appreciation of the communication characteristics is essential to design an efficient interconnection architecture and improve performance. This paper presents a Star network designed for the ePUMA multi-core DSP processor based on analysis of the network communication models. As part of ePUMA’s multi-layer interconnection network, the Star network handles core to off-chip memory communications for kernel computing on slave processors. The network has short setup latency, easy multiprocessor synchronization, rich memory addressing patterns, and power efficient streaming data transfer. The improved network efficiency is evaluated in comparison with a previous study.

Place, publisher, year, edition, pages
IEEE , 2011. 332-336 p.
Keyword [en]
digital signal processing chips;multiprocessor interconnection networks;chip multiprocessor;digital signal processing;ePUMA processor;kernel computing;memory addressing pattern;multicore parallel DSP processor;multilayer interconnection network;multiprocessor synchronization;off-chip memory communication;slave processor;streaming data transfer;streaming star network;Computational modeling;Digital signal processing;Kernel;Memory management;Process control;Vectors;DMA;DSP;multi-core;network-on-chip;streaming signal processin
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-100383DOI: 10.1109/ICNC.2011.64ISBN: 978-1-4577-1796-3 (print)OAI: oai:DiVA.org:liu-100383DiVA: diva2:661719
Conference
Second International Conference on Networking and Computing (ICNC 2011), 30 November - 2 December 2011, Osaka, Japan
Projects
ePUMA
Available from: 2013-11-04 Created: 2013-11-04 Last updated: 2013-11-18Bibliographically approved

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Wang, JianSohl, JoarKarlsson, AndréasLiu, Dake

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Citation style
  • apa
  • harvard1
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Language
  • de-DE
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  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
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  • asciidoc
  • rtf