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ePUMA embedded parallel DSP processor with Unique Memory Access
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
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2011 (English)In: Information, Communications and Signal Processing (ICICS), 2011, IEEE , 2011, 1-5 p.Conference paper, Published paper (Refereed)
Abstract [en]

Computing unto 100GOPS without cooling is essential for high-end embedded systems and much required by markets. A novel master-slave multi-SIMD architecture and its kernel (template) based parallel programming flow is thus introduced as a parallel signal processing platform, ePUMA, embedded Parallel DSP processor with Unique Memory Access. It is an on chip multi-DSP-processor (CMP) targeting to predictable signal processing for communications and multimedia. The essential technologies are to separate the processing of control stream from parallel computing, and to separate parallel data access from parallel arithmetic computing kernels. By separations, the computation and data access can be orthogonal both in hardware and in programs. Orthogonal operations can therefore be executed in parallel and the run time cost of data access can be minimized. Benchmark shows that the computing performance therefore reaches about 80% of the hardware limit. Less than 40% of the hardware limit can be reached by normal processors. The unique SIMD memory subsystem architecture offers programmable conflict free parallel data accesses. Programming flow and tools are also developed to support coding on the unique hardware architecture. A prototype on FPGA shows especially high performance over silicon cost.

Place, publisher, year, edition, pages
IEEE , 2011. 1-5 p.
Keyword [en]
digital signal processing chips;embedded systems;field programmable gate arrays;information retrieval;memory architecture;parallel architectures;parallel programming;SIMD memory subsystem architecture;control stream processing;ePUMA embedded parallel DSP processor;free parallel data access;hardware limit;high-end embedded systems;kernel-based parallel programming flow;master-slave multiSIMD architecture;on chip multiDSP-processor;orthogonal operations;parallel arithmetic computing kernels;parallel computing;parallel data access;parallel signal processing platform;programming tools;unique memory access;Baseband;Computer architecture;Digital signal processing;Kernel;Multimedia communication;Power demand;Silicon;CMP;Kernel;SIMD;ePUMA
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-100382DOI: 10.1109/ICICS.2011.6173516ISBN: 978-1-4577-0029-3 (print)OAI: oai:DiVA.org:liu-100382DiVA: diva2:661720
Conference
8th International Conference on Information, Communications and Signal Processing (ICICS 2011), 13-16 December 2011, Singapore
Projects
ePUMA
Available from: 2013-11-04 Created: 2013-11-04 Last updated: 2013-11-18Bibliographically approved

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Liu, DakeKarlsson, AndréasSohl, JoarPetersson, Magnus

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