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A multi-level arbitration and topology free streaming network for chip multiprocessor
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
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2011 (English)In: ASIC (ASICON), 2011, IEEE , 2011, 153-158 p.Conference paper, Published paper (Refereed)
Abstract [en]

Predictable computing is common in embedded signal processing, which has communication characteristics of data independent memory access and long streaming data transfer. This paper presents a streaming network-on-chip (NoC) StreamNet for chip multiprocessor (CMP) platform targeting predictable signal processing. The network is based on circuit-switch and uses a two-level arbitration scheme. The first level uses fast hardware arbitration, and the second level is programmable software arbitration. Its communication protocol is designed to support free choice of network topology. Associated with its scheduling tool, the network can achieve high communication efficiency and improve parallel computing performance. This NoC architecture is used to design the Ring network in the ePUMA1 multiprocessor DSP. The evaluation by the multi-user signal processing application at the LTE base-station shows the low parallel computing overhead on the ePUMA multiprocessor platform.

Place, publisher, year, edition, pages
IEEE , 2011. 153-158 p.
Keyword [en]
multiprocessing systems;network-on-chip;parallel processing;protocols;scheduling;signal processing;LTE base-station;StreamNet;chip multiprocessor;communication characteristics;communication protocol;data independent memory access;ePUMA multiprocessor platform;ePUMA1 multiprocessor DSP;embedded signal processing;long streaming data transfer;multilevel arbitration;multiuser signal processing;parallel computing performance;programmable software arbitration;ring network;scheduling tool;streaming network-on-chip;topology free streaming network;Bandwidth;Communications technology;Computer architecture;Digital signal processing;Manuals;Software;Switches;Multiprocessor;Network-on-chip;Predictable computing;Streaming network
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-100381DOI: 10.1109/ASICON.2011.6157145ISBN: 978-1-61284-192-2 (print)ISBN: 978-1-61284-191-5 (print)OAI: oai:DiVA.org:liu-100381DiVA: diva2:661722
Conference
IEEE 9th International Conference on ASIC (ASICON 2011), 25-28 October 2011, Xiamen, China
Projects
ePUMA
Available from: 2013-11-04 Created: 2013-11-04 Last updated: 2013-11-18Bibliographically approved

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Wang, JianKarlsson, AndréasSohl, JoarPettersson, MagnusLiu, Dake

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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf