Power consumption is one of the most important design factors in modern electronic design. With a large market increase in portable battery-operated devices and push for environmental focus, it is of interest for the industry to decrease the power consumption of modern chips as much as possible. However, as circuits scale down in size the leakage current increases. This increases the static power consumption, and in future technologies the static power is expected to make up most of the overall power consumption.

Power gating can decrease static power by isolating a circuit block from the power supply. In large chips, this requires state-retention flip flops and non-volatile memories in order to keep the circuit functioning continuously between power gating sequences. A design concept utilizing this is a Normally Off computer, which is in an off-state with no static power for the majority of the time. This is achieved by using non-volatile logic and memories. This concept has been realized by using a new semiconductor technology developed at Semiconductor Energy Laboratories Corporation Ltd., which is known as crystalline In-Ga-Zn oxide semiconductor material. This technology realizes transistors with an ultra-low off-state current, and enables several novel designs of state-retention circuits suitable for Normally-Off computers.

This thesis presents two different architectures of state retention flip flops utilizing In-Ga-Zn oxide semiconductor transistors, which are produced and compared to determine their tradeoffs and effectiveness. These flip flops are then implemented in a 32-bit Normally-Off microprocessor to determine the performance of each implementation. This is evaluated by calculating the energy break-even time, which is the power gating time required to overcome the power overhead introduced by the state-retention flip flops. The resulting circuits and the work in this thesis has been presented at two conferences and submitted for publication in one scientific journal.