liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.ORCID iD: 0000-0002-0111-2384
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2006 (English)In: NORCHIP 2006: The Nordic Microelectronics Event. 2006, 2006, 31-34 p.Conference paper, Published paper (Refereed)
Abstract [en]

Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)

Place, publisher, year, edition, pages
2006. 31-34 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-100922DOI: 10.1109/NORCHP.2006.329238ISBN: 9781424407729 (print)OAI: oai:DiVA.org:liu-100922DiVA: diva2:664338
Conference
24th Norchip Conference, 20-21 November 2006, Linkoping, Sweden.
Available from: 2013-11-14 Created: 2013-11-14 Last updated: 2015-02-18
In thesis
1. Aspects of system-on-chip design for FPGAs
Open this publication in new window or tab >>Aspects of system-on-chip design for FPGAs
2008 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Due to the increasing NRE costs of recent ASICs, the use of FPGAs is expected to continue to increase. While the first FPGAs were limited devices useful mainly for glue logic, todays FPGAs are highly capable devices used in many different application areas including telecommunication, multimedia, medical, and automotive. This means that many VLSI designers need to deal with FPGAs, either as the primary target, or as a prototype platform. The design methodology for an ASIC and FPGA are similar, but if high performance is expected from the FPGA, it is necessary to take FPGA limitations related to memories, data path components, I/O, and routing delays into account early in the design cycle for both FPGA prototyping and FPGA products.

This thesis investigates these limitations through three case studies of important VLSI building blocks. The thesis also discusses how a designer can gain additional information from the FPGA backend flow through custom tools and presents a framework for designing such tools.

The first case study discusses the opportunities and problems when designing both the data path and control path components of a high speed processor in an FPGA. The resulting processor core is a RISC processor with some DSP extensions which has a clock frequency which is significantly higher than the Micro blaze processor which has been specifically developed for Xilinx FPGAs. This case study focuses on the tradeoffs which are necessary to reach this performance in an FPGA.

The second case study describes how a floating point adder and multiplier can be optimized for FPGAs. This is a very important area as the use of floating point arithmetic can significantly reduce the design time of some applications. The solution presented in the thesis outperforms previous academic publications and has a performance similar to commercial offerings.

The third case study presents a packet switched Network-on-Chip (NoC) architecture. While NoCs are not commonly used in FPGA designs today it is expected that they will become an important component in future FPGA designs, especially when prototyping large NoC based ASICs.

Finally, a framework is presented which allows a designer to write custom backend tool by modifying Xilinx XDL files. While the framework is already useful for some tasks, the main reason for including it is to inspire both researchers and developers to look into this area by showing that it is actually quite easy to write such tools.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2008. 72 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1376
Series
LiU-TEK-LIC, 45
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-42791 (URN)68799 (Local ID)978-91-7393-848-8 (ISBN)68799 (Archive number)68799 (OAI)
Presentation
2008-06-13, Sal Glashuset, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-02-18

Open Access in DiVA

No full text

Other links

Publisher's full text

Authority records BETA

Karlström, PerEhliar, AndreasLiu, Dake

Search in DiVA

By author/editor
Karlström, PerEhliar, AndreasLiu, Dake
By organisation
Computer EngineeringThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 227 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf