High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4
2006 (English)In: NORCHIP 2006: The Nordic Microelectronics Event. 2006, 2006, 31-34 p.Conference paper (Refereed)
Since the invention of FPGAs, the increase in their size and performance has allowed designers to use FPGAs for more complex designs. FPGAs are generally good at bit manipulations and fixed point arithmetics but has a harder time coping with floating point arithmetics. In this paper we describe methods used to construct high performance floating point components in a Virtex-4. We have constructed a floating point adder/subtracter and multiplier which we then used to construct a complex radix-2 butterfly. Our adder/subtracter can operate at a frequency of 361 MHz in a Virtex-4SX35 (speed grade -12)
Place, publisher, year, edition, pages
2006. 31-34 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-100922DOI: 10.1109/NORCHP.2006.329238ISBN: 9781424407729OAI: oai:DiVA.org:liu-100922DiVA: diva2:664338
24th Norchip Conference, 20-21 November 2006, Linkoping, Sweden.