Switched interconnect for system-on-a-chip design
2000 (English)In: Proceedings of the IP2000 Europe Conference, 2000, 185-192 p.Conference paper (Other academic)
With the increased use of IP cores in chip designs, an increasing amount of time is spent on design and verification of glue logic. To solve this problem together with the bottleneck problem of arbitration based buses, a novel approach in system-on-a-chip interconnect has been investigated. The approach is based on a switched interconnect structure, with small crossbar switches connected in a mesh for intercore communications with low latency in system-on-chip solutions. The interfaces between the interconnect network and the cores are handled by configurable wrappers that adapt the port parameters from core to network format. The core functionality of the interconnect network can be fully verified with a fairly low work effort even when configurable, so the main problem for cutting verification time is the quite complex wrappers. The concept is to make the wrappers highly configurable yet needing short verification time in an application by making a fairly complete verification of the wrappers for all configurations. How this can be achieved is under investigation. The approach described in this paper is mainly aimed for use in communication equipment where high bandwidth and low latency is essential.
Place, publisher, year, edition, pages
2000. 185-192 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-100987OAI: oai:DiVA.org:liu-100987DiVA: diva2:664654
IP2000 Europe Conference. Edinburgh, Scotland, 2000