liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Switched interconnect for system-on-a-chip design
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2000 (English)In: Proceedings of the IP2000 Europe Conference, 2000, 185-192 p.Conference paper, Published paper (Other academic)
Abstract [en]

With the increased use of IP cores in chip designs, an increasing amount of time is spent on design and verification of glue logic. To solve this problem together with the bottleneck problem of arbitration based buses, a novel approach in system-on-a-chip interconnect has been investigated. The approach is based on a switched interconnect structure, with small crossbar switches connected in a mesh for intercore communications with low latency in system-on-chip solutions. The interfaces between the interconnect network and the cores are handled by configurable wrappers that adapt the port parameters from core to network format. The core functionality of the interconnect network can be fully verified with a fairly low work effort even when configurable, so the main problem for cutting verification time is the quite complex wrappers. The concept is to make the wrappers highly configurable yet needing short verification time in an application by making a fairly complete verification of the wrappers for all configurations. How this can be achieved is under investigation. The approach described in this paper is mainly aimed for use in communication equipment where high bandwidth and low latency is essential.

Place, publisher, year, edition, pages
2000. 185-192 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-100987OAI: oai:DiVA.org:liu-100987DiVA: diva2:664654
Conference
IP2000 Europe Conference. Edinburgh, Scotland, 2000
Available from: 2013-11-15 Created: 2013-11-15 Last updated: 2013-11-15
In thesis
1. An on-chip network architecture for hard real time systems
Open this publication in new window or tab >>An on-chip network architecture for hard real time systems
2003 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

With the ever increasing demands on processing power and communication on a single chip the industry is facing a huge obstacle in closing the gap between possible complexity and achieved complexity, the so called design gap. A possible path out of this is the increase (re-)use of intellectual property (IP) blocks from within the company or from other suppliers. We have identified the problem area in the on-chip communication between IP blocks where the time-division multiplex buses are quickly becoming saturated.

Another problem arising with the increased use of deep submicron manufacturing technologies is the relatively long delay of wires compared to the gates. This problem forces the synchronous part of a chip to either shrink or run at a slower speed. With the goals of keeping the clock rate and increasing the complexity the only feasible solution is to use smaller synchronous subsystems that communicate asynchronously. This approach is known as globally asynchronous but locally synchronous (GALS).

This thesis presents the work on a bus replacement for on-chip communication. The goal of this bus replacement is to achieve very high performance compared to the old solution while allowing for higher flexibility, GALS style implementation, and simpler verification of the system.

With this goal in mind we investigated the possible topologies for a switched on-chip network (OCN) and concluded that a 2-d mesh or torus is the most appropriate. To keep the latency low we decided on a pseudo-circuit switched network using the 2-d mesh. We have developed a novel approach for route setup in the circuit switched network called packet connected circuit (PCC) which allows very short latency both for routing and payload transfer while having a very low silicon cost.

A simulator for this network has been implemented together with behavioral models of the network components. Simulations have shown that the PCC concept is not very suitable for general purpose processing platforms but that it is very suitable for a hard real time system that uses some communication scheduling.

Place, publisher, year, edition, pages
Linköping: Inivserv, 2003. 37 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 996
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33279 (URN)19279 (Local ID)91-7373-577-9 (ISBN)19279 (Archive number)19279 (OAI)
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-15

Open Access in DiVA

No full text

Other links

http://www.da.isy.liu.se/pubs/danwi/danwi-ip2000.pdf

Authority records BETA

Wiklund, DanielLiu, Dake

Search in DiVA

By author/editor
Wiklund, DanielLiu, Dake
By organisation
Computer EngineeringThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric score

urn-nbn
Total: 186 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf