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A Fault-Aware Resource Manager for Multi-Processor System-on-Chip
Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology. (ESLAB)
2013 (English)Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
Abstract [en]

The semiconductor technology development empowers fabrication of extremelycomplex integrated circuits (ICs) that may contain billions of transistors. Suchhigh integration density enables designing an entire system onto a single chip,commonly referred to as a System-on-Chip (SoC). In order to boost performance,it is increasingly common to design SoCs that contain a number of processors, socalled multi-processor system-on-chips (MPSoCs).While on one hand, recent semiconductor technologies enable fabrication ofdevices such as MPSoCs which provide high performance, on the other hand thereis a drawback that these devices are becoming increasingly susceptible to faults.These faults may occur due to escapes from manufacturing test, aging effects orenvironmental impacts. When present in a system, faults may disrupt functionalityand can cause incorrect system operation. Therefore, it is very importantwhen designing systems to consider methods to tolerate potential faults. To copewith faults, there is a need of fault handling which implies automatic detection,identification and recovery from faults which may occur during the system’s operation.This work is about the design and implementation of a fault handling methodsfor an MPSoC. A fault aware Resource Manager (RM) is designed and implementedto obtain correct system operation and maximize the system’s throughputin the presence of faults. The RM has the responsibility of scheduling jobs to availableresources, collecting fault states from resources in the system and performingfault handling tasks, based on fault states. The RM is also employed in multipleexperiments in order to study its behavior in different situations.

Place, publisher, year, edition, pages
2013. , 56 p.
Keyword [en]
Fault tolerance, Resource manager, Threshold
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-101010ISRN: LIU-IDA/LITH-EX-A--13/055--SEOAI: oai:DiVA.org:liu-101010DiVA: diva2:664776
Subject / course
Computer and information science at the Institute of Technology
Supervisors
Examiners
Available from: 2013-11-18 Created: 2013-11-17 Last updated: 2013-11-18Bibliographically approved

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Hoda_ghaeini_master_thesis(2050 kB)143 downloads
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Department of Computer and Information ScienceThe Institute of Technology
Engineering and Technology

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf