High-speed, low latency, digital, one bit input FIR-filter implementation
(English)Manuscript (preprint) (Other academic)
This paper present a low latency, one bit input, high-speed FIR-filter implementation designed for high-speed mixed signal decision feedback equalizers. The filter structure features a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer implementation. The filter has been implemented in a standard 0.13μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency < 270 ps.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-102637OAI: oai:DiVA.org:liu-102637DiVA: diva2:680170