Sampling error minimization using a differential bootstrapped sampler
2001 (English)In: Proceedings of the SSoCC'01, 2001Conference paper (Other academic)
This paper presents a novel bootstrap technique implemented in a fully-differential sampler. The main sampling errors are discussed and the sampling time variation for the bootstrapped sampler is derived. The proposed bootstrap sampler is compared with an ordinary sampler to show an improvement in SFDR. A differential clock sampling is introduced to minimize the sampling error due to noise in clock and power supply. Simulation results show significant improvement in sampling accuracy.
Place, publisher, year, edition, pages
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-102672OAI: oai:DiVA.org:liu-102672DiVA: diva2:680748
Swedish System-on-Chip Conference 2001, Arild, Sweden. 20-21/3 2001