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Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 2, 358-370 p.Article in journal (Refereed) Published
Abstract [en]

A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

Place, publisher, year, edition, pages
IEEE , 2014. Vol. 61, no 2, 358-370 p.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-102756DOI: 10.1109/TCSI.2013.2278346ISI: 000331191800004OAI: oai:DiVA.org:liu-102756DiVA: diva2:681772
Available from: 2013-12-20 Created: 2013-12-20 Last updated: 2017-12-06Bibliographically approved
In thesis
1. Low-Power Delta-Sigma Modulators for Medical Applications
Open this publication in new window or tab >>Low-Power Delta-Sigma Modulators for Medical Applications
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Biomedical electronics has gained significant attention in healthcare. A general biomedical device comprises energy source, analog-to-digital conversion (ADC), digital signal processing, and communication subsystem, each of which must be designed for minimum energy consumption to adhere to the stringent energy constraint.

The ADC is a key building block in the sensing stage of the implantable biomedical devices. To lower the overall power consumption and allow full integration of a complete biomedical sensor interface, it is desirable to integrate the entire analog front-end, back-end ADC and digital processor in a single chip. While digital circuits benefit substantially from the technology scaling, it is becoming more and more difficult to meet the stringent requirements on linearity, dynamic range, and power-efficiency at lower supply voltages in traditional ADC architectures. This has recently initiated extensive investigations to develop low-voltage, lowpower, high-resolution ADCs in nanometer CMOS technologies. Among different ADCs, the ΔΣ converter has shown to be most suitable for high-resolution and low-speed applications due to its high linearity feature.

This thesis investigates the design of high-resolution and power-efficient ΔΣ modulators at very low frequencies. In total, eight discrete-time (DT) modulators have been designed in a 65nm CMOS technology: two active modulators, two hybrid active-passive modulators, two ultra-low-voltage modulators operated at 270mV and 0.5V supply voltages, one fully passive modulator, and a dual-mode ΔΣ modulator using variable-bandwidth amplifiers.

The two active modulators utilize traditional feedback architecture. The first design presents a simple and robust low-power second-order ΔΣ modulator for accurate data conversion in implantable rhythm management devices such as cardiac pacemakers. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-Vth devices in analog circuits and switches. An 80dB SNR (13-bit) was achieved at the cost of 2.1μW power in 0.033mm2 chip core area. The second design introduces a third-order modulator adopting the switched-opamp and partially body-driven gain-enhanced techniques in the OTAs for low-voltage and low-power consumption. The modulator achieves 87dB SNDR over 500Hz signal bandwidth, consuming 0.6μW at 0.7V supply.

The two hybrid modulators were designed using combined SC active and passive integrators to partially eliminate the analog power associated with the active blocks. The first design employs an active integrator in the 1st stage and a passive integrator in the less critical 2nd stage. A 73.5dB SNR (12-bit) was achieved at the cost of 1.27μW power in a 0.059mm2 chip core area. The latter modulator utilizes a fourth-order active-passive loop filter with only one active stage. The input-feedforward architecture is used to improve the voltage swing prior to the comparator of the traditional passive modulators, which enables a simpler comparator design without requiring a preamplifier. It also allows the use of three successive passive filters to obtain a higher-order noise shaping. The modulator attains 84dB SNR while dissipating 0.4μW power at a 0.7V supply.

Two ultra-low-voltage DT modulators operating at 0.5V and the state-of-the-art 270mV power supplies were proposed. The former modulator employs fully passive loop filter followed by a 0.5V preamplifier and dynamic comparator, whereas the latter one exploits the inverter-based integrators combined with clock boosting scheme for adequate switches overdrive voltage. The first design incorporates a gain-boosted scheme using charge redistribution amplification in the passive filter as well as a body-driven gain-enhanced preamplifier prior to the comparator in order to compensate for the gain shortage. It attains 75dB SNR consuming 250nW power, which is a record amongst the state-of-the-art ultra-lowpower ΔΣ modulators. The second design uses feedforward architecture that suggests low integrators swing, enabling ultra-low-voltage operation. The degraded gain, GBW and SR of the inverter amplifiers operating at such a low voltage are enhanced by a simple current-mirror output stage. The attained FOM is 0.31pJ/step.

A fully passive DT modulator was presented aiming for analog power reduction, the dominant part of the power in the active modulators. A careful analysis of the non-idealities in the passive filter, including the noise, parasitic effect, and integrator’s leakage were essential to meet the performance requirement necessary for an implantable device. The chip was tested simultaneously with its active counterpart, showing significant power reduction at the cost of 4× core area and 12dB SNR loss.

The designed dual-mode modulator employs variable-bandwidth amplifiers in combination with oversampling ratio to provide tunable resolution. This work presents the design, implementation, and test results of a two-stage amplifier using the second stage replica, that provides tunable GBW with consistent DC gain.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. 124 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1563
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-102903 (URN)10.3384/diss.diva-102903 (DOI)978-91-7519-446-2 (ISBN)
Public defence
2014-01-21, Visionen, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2014-01-07 Created: 2014-01-07 Last updated: 2014-01-27Bibliographically approved
2. Selected Applications of Switched Capacitor Circuits: RF N-Path Filters and ΣΔ Modulators
Open this publication in new window or tab >>Selected Applications of Switched Capacitor Circuits: RF N-Path Filters and ΣΔ Modulators
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Electronic circuits based on switches and capacitors have been used in various applications for several decades. The common switched capacitor (SC) circuits have made their career primarily in analog filters and data converters due to high immunity to capacitance mismatch in integrated circuit (IC) technologies. Recently, also in other fields, circuits using switches and capacitors appeared very attractive. In particular, tunable sampling receiver frontends and N-path RF filters have proven very useful; the latter as a tunable integrated replacement for surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters. In this work addressed are applications of SC technique in ΣΔ modulators and RF bandpass filters.

In a typical receiver frontend the SAW or BAW filters are placed after the antenna to suppress the out-of-band interferers (OBI) that can have power levels as high as 0 dBm. These filters by their nature are neither tunable over frequency nor programmable for different bandwidths. Recently, several SAW-less receivers have been proposed based on the idea of N-path filters that are built with switches and capacitors and driven by N-phase non-overlapping clock. N-path filters make use of baseband impedance upconversion and are tunable with clock frequency. However, with capacitors at baseband, the resulting second order RF filter can only provide a limited blocker rejection.

The first contribution of this work is a tunable zero-IF receiver font-end which employs two 4-path bandpass filters in cascade that operate over the frequency range of (0.5-3) GHz. Each filter section is composed of low noise trans-conductance amplifier (LNTA) and a 4-path structure based on switches and capacitors. The second stage also serves as a downconversion mixer in this architecture. In order to avoid loading effects and thereby guarantee high blocker rejection, a voltage buffer is placed between the stages. The 4-path filter gain is estimated by linear periodically varying (LPV) model which accurately captures the RF filter gain in the presence of parasitic capacitance of the amplifier and the switches. The model is also suited to account for the possible clock phase mismatch effects. Fabricated in CMOS 65 nm technology the measured frontend has achieved out-of-band IIP3 and out-of-band P1dB of +15 dBm and +5 dBm respectively. The NF varies from 3.2 to 5.3 dB at 0.5 GHz to 3 GHz. A blocker rejection of 60 dB is achieved at 0.5 GHz which reduces gradually with frequency to 38 dB at 3 GHz.

Another technique suitable for high rejection filtering at RF is based on subtraction of two bandpass filter responses with slightly different center frequencies. Combining the frequency responses in this way also results in better shaping of the filter passband. The necessary offset frequency can be obtained with one clock frequency and quadrature coupled virtual LC tanks at baseband using gm − C cells. In this work the N-path filter is adopted to serve in a low-IF receiver frontend where the effect of 1/f noise of gm cells can be mitigated. For this purpose, the offset frequencies of both filter branches are chosen to be either positive or negative against the carrier. In this setup the filter is also used as a quadrature downconversion mixer. Importantly, some image rejection is already achieved at RF and it is upto 15 dB after downconversion to IF, relaxing thereby the demands for the ultimate image rejection. Simulated in 65 nm CMOS technology the frontend achieves out-of-band IIP3 of 8 dBm, NF of less than 6 dB while image rejection (IR) at RF and IF is 4.8 dB and 15 dB, respectively.

Another contribution of this work is the design of passive SC ΣΔ modulators for low frequency applications. A low frequency ultra-low-power passive modulator was designed in 65 nm CMOS technology and by exploring the design space it was optimized for signal-to-noise and distortion ratio (SNDR). Using a second order SC filter the modulator demonstrated in measurements SNDR = 67 dB and a figure of merit (FOM) of 0.296 pJ/step, which in a comparative design study was superior to its counterparts, semi-passive and active SC ΣΔ modulators.

Furthermore the analysis and design procedures of passive SC ΣΔ modulator are revisited. Presented is the optimization of the noise transfer function (NTF) of second order passive SC modulator in the design space defined by the filter capacitor ratios and the feedback coefficients. Included is a detailed analysis of the thermal noise of the loop filter and the quantizer. Quantization noise, and other parasitic effects are thoroughly analyzed as well. After the optimization, high level simulations show good compliance with the measurement results. Peak SNDR of 73.7/68.4 dB, DR of 73.4/70.7 dB and MSA of -6.6/-4.3 dBFS is measured in 65 nm CMOS process for the sampling frequency of 500 kHz/250 kHz, respectively, while the attained minimum FOM is 0.17 pJ/step.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. 63 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1627
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112882 (URN)978-91-7519-210-9 (ISBN)
Public defence
2015-01-14, Signalen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2016-01-18Bibliographically approved

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Fazli Yeknami, AliQazi, FahadAlvandpour, Atila

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