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Low-Power Delta-Sigma Modulators for Medical Applications
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Biomedical electronics has gained significant attention in healthcare. A general biomedical device comprises energy source, analog-to-digital conversion (ADC), digital signal processing, and communication subsystem, each of which must be designed for minimum energy consumption to adhere to the stringent energy constraint.

The ADC is a key building block in the sensing stage of the implantable biomedical devices. To lower the overall power consumption and allow full integration of a complete biomedical sensor interface, it is desirable to integrate the entire analog front-end, back-end ADC and digital processor in a single chip. While digital circuits benefit substantially from the technology scaling, it is becoming more and more difficult to meet the stringent requirements on linearity, dynamic range, and power-efficiency at lower supply voltages in traditional ADC architectures. This has recently initiated extensive investigations to develop low-voltage, lowpower, high-resolution ADCs in nanometer CMOS technologies. Among different ADCs, the ΔΣ converter has shown to be most suitable for high-resolution and low-speed applications due to its high linearity feature.

This thesis investigates the design of high-resolution and power-efficient ΔΣ modulators at very low frequencies. In total, eight discrete-time (DT) modulators have been designed in a 65nm CMOS technology: two active modulators, two hybrid active-passive modulators, two ultra-low-voltage modulators operated at 270mV and 0.5V supply voltages, one fully passive modulator, and a dual-mode ΔΣ modulator using variable-bandwidth amplifiers.

The two active modulators utilize traditional feedback architecture. The first design presents a simple and robust low-power second-order ΔΣ modulator for accurate data conversion in implantable rhythm management devices such as cardiac pacemakers. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-Vth devices in analog circuits and switches. An 80dB SNR (13-bit) was achieved at the cost of 2.1μW power in 0.033mm2 chip core area. The second design introduces a third-order modulator adopting the switched-opamp and partially body-driven gain-enhanced techniques in the OTAs for low-voltage and low-power consumption. The modulator achieves 87dB SNDR over 500Hz signal bandwidth, consuming 0.6μW at 0.7V supply.

The two hybrid modulators were designed using combined SC active and passive integrators to partially eliminate the analog power associated with the active blocks. The first design employs an active integrator in the 1st stage and a passive integrator in the less critical 2nd stage. A 73.5dB SNR (12-bit) was achieved at the cost of 1.27μW power in a 0.059mm2 chip core area. The latter modulator utilizes a fourth-order active-passive loop filter with only one active stage. The input-feedforward architecture is used to improve the voltage swing prior to the comparator of the traditional passive modulators, which enables a simpler comparator design without requiring a preamplifier. It also allows the use of three successive passive filters to obtain a higher-order noise shaping. The modulator attains 84dB SNR while dissipating 0.4μW power at a 0.7V supply.

Two ultra-low-voltage DT modulators operating at 0.5V and the state-of-the-art 270mV power supplies were proposed. The former modulator employs fully passive loop filter followed by a 0.5V preamplifier and dynamic comparator, whereas the latter one exploits the inverter-based integrators combined with clock boosting scheme for adequate switches overdrive voltage. The first design incorporates a gain-boosted scheme using charge redistribution amplification in the passive filter as well as a body-driven gain-enhanced preamplifier prior to the comparator in order to compensate for the gain shortage. It attains 75dB SNR consuming 250nW power, which is a record amongst the state-of-the-art ultra-lowpower ΔΣ modulators. The second design uses feedforward architecture that suggests low integrators swing, enabling ultra-low-voltage operation. The degraded gain, GBW and SR of the inverter amplifiers operating at such a low voltage are enhanced by a simple current-mirror output stage. The attained FOM is 0.31pJ/step.

A fully passive DT modulator was presented aiming for analog power reduction, the dominant part of the power in the active modulators. A careful analysis of the non-idealities in the passive filter, including the noise, parasitic effect, and integrator’s leakage were essential to meet the performance requirement necessary for an implantable device. The chip was tested simultaneously with its active counterpart, showing significant power reduction at the cost of 4× core area and 12dB SNR loss.

The designed dual-mode modulator employs variable-bandwidth amplifiers in combination with oversampling ratio to provide tunable resolution. This work presents the design, implementation, and test results of a two-stage amplifier using the second stage replica, that provides tunable GBW with consistent DC gain.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. , 124 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1563
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-102903DOI: 10.3384/diss.diva-102903ISBN: 978-91-7519-446-2 (print)OAI: oai:DiVA.org:liu-102903DiVA: diva2:684165
Public defence
2014-01-21, Visionen, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2014-01-07 Created: 2014-01-07 Last updated: 2014-01-27Bibliographically approved
List of papers
1. A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS
Open this publication in new window or tab >>A 2.1 mu W 80 dB SNR DT Delta I pound modulator for medical implant devices in 65 nm CMOS
2013 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 77, no 1, 69-78 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a simple and robust low-power Delta I pound modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V-T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 mu W, the modulator obtains 0.4 pJ/step FOM. To the authors knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order Delta I pound modulators.

Place, publisher, year, edition, pages
Springer, 2013
Keyword
Analog-to-digital converter (ADC), Delta-sigma modulator, Operational transconductance amplifier (OTA), Medical implant device Load-compensated two-stage amplifier
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-100027 (URN)10.1007/s10470-013-0087-x (DOI)000324828000007 ()
Conference
The 30th NORCHIP conference, November 12, Copenhagen, Denmark
Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2017-12-06Bibliographically approved
2. Design of OTAs for ultra-low-power sigma-delta ADCs in medical applications
Open this publication in new window or tab >>Design of OTAs for ultra-low-power sigma-delta ADCs in medical applications
2010 (English)In: International Conference on Signals and Electronic Systems, IEEE , 2010, 229-232 p.Conference paper, Published paper (Refereed)
Abstract [en]

High-resolution sigma-delta ADCs are gaining significant interest in ultra-low-power medical applications, where accurate measurement of low-frequency and weak electrophysiological signals is required. Operational transconductance amplifiers (OTA) are the key analog component and the most power-hungry part of the sigma-delta (ΣA) modulators. This paper presents a study of OTAs for ultra-low-power operation, including design and a comparative analysis of four OTA architectures implemented in 65nm CMOS Technology. The requirements for OTA gain and GBW are driven in terms of ΣA ADC specifications. The OTAs' impact on modulator SNR has been investigated by simulation. The results show that a two-stage OTA with load compensation yields highest SNR and lowest power dissipation amongst the four OTAs in this study.

Place, publisher, year, edition, pages
IEEE, 2010
Keyword
CMOS integrated circuits, bioelectric phenomena, biomedical electronics, biomolecular electronics, low-power electronics, operational amplifiers, sigma-delta modulation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-65455 (URN)978-1-4244-5307-8 (ISBN)
Conference
IEEE International Conference on Signal and Electronic Systems, September 7-10, Gliwice, Poland
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2014-01-07Bibliographically approved
3. A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition
Open this publication in new window or tab >>A 0.7-V 600-nW 87-dB SNDR DT-Delta Sigma Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition
2012 (English)In: 2012 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS): INTELLIGENT BIOMEDICAL ELECTRONICS AND SYSTEM FOR BETTER LIFE AND BETTER ENVIRONMENT, IEEE , 2012, 336-339 p.Conference paper, Published paper (Refereed)
Abstract [en]

A 0.7 V third-order DT Delta Sigma modulator is presented in this paper for measurement of biopotential signals in portable medical applications. Switched-opamp technique has been adopted in this design to eliminate the critical switches, which leads to low-voltage and low-power consumption. The modulator employs new partially body-driven gain-enhanced amplifiers for low-voltage operation in order to compensate the dc gain degradation. Switched-opamp approach is embedded in amplifiers and CMFB circuits to reduce the power consumption. The major building blocks, such as the proposed Class AB gain-enhanced amplifiers and the low-voltage comparator, use body-biased p-MOS to reduce the threshold voltage, thus providing more voltage headroom in the low voltage environment. Noise analysis, as a critical step in the design of a high resolution ADC, is also provided. Designed in a 65nm CMOS technology, the modulator achieves 87 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 600-nW from a 0.7 V supply.

Place, publisher, year, edition, pages
IEEE, 2012
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-96534 (URN)10.1109/BioCAS.2012.6418428 (DOI)000316563200099 ()978-1-4673-2291-1 (ISBN)
Conference
IEEE Biomedical Circuits and Systems Conference (BioCAS 2012), 28-30 November 2012, Hsinchu, Taiwan
Available from: 2013-08-21 Created: 2013-08-20 Last updated: 2014-01-07Bibliographically approved
4. A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices
Open this publication in new window or tab >>A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices
2013 (English)In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013, 2013, 2010-2013 p.Conference paper, Published paper (Refereed)
Abstract [en]

A  0.5-V  ultra-low-power  second-order  DT  DS  modulator  is  presented  in  this  paper  for  medical  implant  devices.  The  modulator  employs  2nd-order  passive  low-pass filter  and  ultra-low-voltage  building  blocks,  including preamplifier, regenerative comparator, and clock controller, in order  to enable operation near 0.5 V supply. A  low-noise and gain-enhanced  single-stage  preamplifier  is  developed  using  a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification  scheme. Designed in  a  65nm CMOS  technology,  the modulator  achieves  65  dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW  from  a  0.5 V  supply. The modulator  is  functional  at 0.45V and obtains 52 dB SNR, while consuming 200 nW.

Series
IEEE International Symposium on Circuits and Systems (ISCAS), 2013, ISSN 0271-4302 ; 2013
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-97263 (URN)10.1109/ISCAS.2013.6572265 (DOI)000332006802059 ()978-1-4673-5760-9 (ISBN)
Conference
The IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013
Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2014-05-12Bibliographically approved
5. A 270-mV  ΔΣ Modulator Using Gain-Enhanced, Inverter-Based Amplifier
Open this publication in new window or tab >>A 270-mV  ΔΣ Modulator Using Gain-Enhanced, Inverter-Based Amplifier
2013 (English)Manuscript (preprint) (Other academic)
Abstract [en]

An ultra-low-voltage low-power switched-capacitor ΔΣ modulator running at a supply voltage as low as 270 mV is presented for medical implant devices. To reduce the supply voltage and power consumption, an inverter-based amplifier is used in the integrator, whose DC-gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. The entire modulator operates at 270 mV supply only, while the switches are driven by charge pump clock doubler. Designed in 65 nm CMOS and clocked at 256 kHz, the simulation results show that the converter achieves 64.4 dB signal-to-noise-ratio (SNR) and 61 dB signal-to-noise-and-distortionratio (SNDR) in 1 kHz bandwidth while consuming 0.85 "W power.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-102896 (URN)
Available from: 2014-01-07 Created: 2014-01-07 Last updated: 2014-01-07Bibliographically approved
6. Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
Open this publication in new window or tab >>Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 2, 358-370 p.Article in journal (Refereed) Published
Abstract [en]

A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-102756 (URN)10.1109/TCSI.2013.2278346 (DOI)000331191800004 ()
Available from: 2013-12-20 Created: 2013-12-20 Last updated: 2017-12-06Bibliographically approved
7. A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage
Open this publication in new window or tab >>A 0.7-V 400-nW Fourth-Order Active-Passive Delta-Sigma Modulator with One Active Stage
2013 (English)Conference paper, Published paper (Refereed)
Abstract [en]

A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator's noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

Place, publisher, year, edition, pages
IEEE, 2013
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-97265 (URN)10.1109/VLSI-SoC.2013.6673235 (DOI)000332046100001 ()
Conference
IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 7-9 October, Istanbul, Turkey
Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2014-04-04Bibliographically approved
8. A Programmable-Bandwidth Amplifier for Ultra-Low-Power Switched-Capacitor Application
Open this publication in new window or tab >>A Programmable-Bandwidth Amplifier for Ultra-Low-Power Switched-Capacitor Application
2011 (English)In: IEEE European Conference on Circuit Theory and Design (ECCTD), IEEE conference proceedings, 2011, 761-764 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a novel approach to design a programmable-bandwidth amplifier intended for ultra-low-power switched-capacitor application. The proposed topology is based on the common load-compensated two-stage OTA. The GBW is enhanced by replicating the second amplifying stage. Implemented in a 65-nm CMOS technology and approved by the post-layout simulation, the GBW is programmed in three operation modes (400, 700, and 900 kHz), while 52-dB DC gain is preserved in a 5-pF load. The OTA consumes 275-nW static power in a 400 kHz unity-gain frequency and 375-nW static power in a 900 kHz unity-gain frequency from 0.9-V supply.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2011
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-73029 (URN)10.1109/ECCTD.2011.6043849 (DOI)978-1-4577-0617-2 (ISBN)978-1-4577-0616-5 (ISBN)
Conference
20th European Conference on Circuit Theory and Design, Linköping, 29-31 August, Linköping, Sweden
Available from: 2011-12-14 Created: 2011-12-14 Last updated: 2014-01-07Bibliographically approved
9. A Variable Bandwidth Amplifier for a Dual-mode Low-Power ΔΣ Modulator in Cardiac Pacemaker System
Open this publication in new window or tab >>A Variable Bandwidth Amplifier for a Dual-mode Low-Power ΔΣ Modulator in Cardiac Pacemaker System
2013 (English)In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2013, 1918-1921 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the design and implementation of a variable bandwidth amplifier intended for ultra-low-power biomedical implants in 65nm CMOS, providing tunable gain-bandwidth in three modes: 0.9 MHz, 1.7 MHz, and 2.3 MHz with consistent 56 dB DC gain. The amplifier consumes 180nW static power in the lowest bandwidth mode, and consumes 315 nW static power in the full bandwidth mode with an 8 pF load from a 0.9-V supply voltage. To illustrate the concept, the presented programmable bandwidth amplifier is applied in a dual-mode ΔΣ modulator aiming for sensing/measuring stage of a cardiac pacemaker.

Series
IEEE International Symposium on Circuits and Systems (ISCAS), ISSN 0271-4302 ; 2013
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-97264 (URN)10.1109/ISCAS.2013.6572242 (DOI)000332006802036 ()978-1-4673-5760-9 (ISBN)
Conference
The IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May, 2013
Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2014-05-12Bibliographically approved

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Publisher's full textLink to article: A 2.1 µW 76 dB SNDR DT Delta-Sigma Modulator for Medical Implant DevicesLink to article: Design of OTAs for Ultra-Low-Power Sigma-Delta ADCs in Medical Applications

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Fazli Yeknami, Ali

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