Highly linear open-loop output driver design for high speed capacitive DACs
2013 (English)In: 2013 NORCHIP, 11–12 November, 2013, Vilnius, LITHUANIA, 2013, 1-4 p.Conference paper (Refereed)
Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the resistive source degeneration resulting in HD3 <; -70 dB and HD2 <; -90 dB over the band of 0.5-4 GHz in 65-nm CMOS. For the output swing of 300 mVpp and 1.2 V supply its power consumption is 40 mW. For verification the driver is implemented in a 12-bit pipeline SC DAC. In simulations the complete Nyquist-rate DAC achieves SFDR of 64 dB for signal bandwidth up to 2.2 GHz showing a negligible non-linearity contribution by the designed driver for signal frequencies up to 1.3 GHz and a degradation by 3 dB at 2.2 GHz.
Place, publisher, year, edition, pages
2013. 1-4 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-102930DOI: 10.1109/NORCHIP.2013.6702039ISBN: 9781479916474OAI: oai:DiVA.org:liu-102930DiVA: diva2:684518
31st Norchip Conference, 11-12 November 2013, Vilnius, Lithuania