RF Calibration of On-Chip DfT Chain by DC Stimuli and Statistical Multivariate Regression Technique
2015 (English)In: Integration, ISSN 0167-9260, Vol. 49, 14-21 p.Article in journal (Refereed) Published
The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a general RF calibration scheme using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error in DfT circuit response can be reduced to 2.5% for input stimuli in excess of 500mV. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.
Place, publisher, year, edition, pages
Elsevier, 2015. Vol. 49, 14-21 p.
DfT, On-chip RF detector, RF BIST, RF calibration, RF DfT, RF testing, ANN application
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-105514DOI: 10.1016/j.vlsi.2014.11.006ISI: 000351018200002OAI: oai:DiVA.org:liu-105514DiVA: diva2:707842