1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS
2014 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 22, no 4, 888-898 p.Article in journal (Refereed) Published
This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 mu V DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2014. Vol. 22, no 4, 888-898 p.
Analog-to-digital conversion (ADC); CMOS analog integrated circuits (ICs); HDTV; MOSFET switches; programmable gain amplifiers (PGAs); video AFEs
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-106124DOI: 10.1109/TVLSI.2013.2252635ISI: 000333354400017OAI: oai:DiVA.org:liu-106124DiVA: diva2:714042