A quadrature UWB frequency synthesizer with dynamic settling-time calibration
2013 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE , 2013, 2480-2483 p.Conference paper (Refereed)
This paper presents a quadrature DLL-based architecture for WiMedia ultra-wideband (UWB) frequency synthesis. I and Q carriers are directly generated by combining the quadrature multi-phase outputs of the DLL, using separate edge combiners (EC). A variable-stage voltage-controlled delay line (VCDL) scheme is proposed to provide the corresponding output phases to each EC, without the need for multiplexing the DLL outputs for different bands. Moreover, to prevent possible synthesizer hopping time degradation due to dynamic variations in temperature and voltage, a monitoring mechanism is employed to measure the time error at the instant of band switching, and compensate for it if it is beyond a limited value. The Synthesizer is implemented in a standard 65-nm CMOS technology and the simulation results indicate a hopping time of 4.5 to 8.8 ns across process corners. Simulated phase noise at 1 MHz offset from 4488 MHz carrier is -115 dBc/Hz and the worst case spur suppression is -31 dBc. The synthesizer consumes 13.9 mA from a 1.2-V supply.
Place, publisher, year, edition, pages
IEEE , 2013. 2480-2483 p.
, Circuits and Systems (ISCAS), ISSN 0271-4302
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-106536DOI: 10.1109/ISCAS.2013.6572382ISI: 000332006802174ISBN: 978-1-4673-5760-9OAI: oai:DiVA.org:liu-106536DiVA: diva2:716594
2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013; Beijing; China