Pipelined parallel sorting on the Intel SCC
2011 (English)In: Fourth Swedish Workshop on Multi-Core Computing MCC-2011: November 23-25, 2011, Linköping University, Linköping, Sweden / [ed] Christoph Kessler, Linköping: Linköping University , 2011, Vol. S. 96-101, 96-101 p.Conference paper (Other academic)
The Single-Chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. It comprises 48 Intel-IA32 cores linked by an on-chip high performance mesh network, as well as four DDR3 memory controllers to access an off-chip main memory. We investigate the adaptation of sorting onto SCC as an algorithm engineering problem. We argue that a combination of pipelined mergesort and sample sort will fit best to SCC's architecture. We also provide a mapping based on integer linear programming to address load balancing and latency considerations. We describe a prototype implementation of our proposai together with preliminary runtime measurements, that indicate the usefulness of this approach. As mergesort can be considered as a representative of the class of streaming applications, the techniques deveioped here should also apply to the other problems in this class, such as many applications for parallel embedded systems, i.e. MPSoC.
Place, publisher, year, edition, pages
Linköping: Linköping University , 2011. Vol. S. 96-101, 96-101 p.
IdentifiersURN: urn:nbn:se:liu:diva-106591OAI: oai:DiVA.org:liu-106591DiVA: diva2:716879
Swedish Workshop on Multi-Core Computing