Built-in self-test of analog-to-digital converters in FPGAs
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
When designing an ADC it is desirable to test its performance at two different points in the development process. The first is characterization and verification testing when a chip containing the ADC has been taped-out for the first time, and the second is production testing when the chip is manufactured in large scale. It is important to have a good correlation between the results of characterization and the results of production testing.
This thesis project investigates the feasibility of using a built-in self-test to evaluate the performance of embedded ADCs in FPGAs, by using the FPGA fabric to run necessary test algorithms. The idea is to have a common base of C code for both characterization and production testing. The code can be compiled and run on a computer for a characterization test setup, but it can also be synthesized using a high-level synthesis (HLS) tool, and written to FPGA fabric as part of a built-in self-test for production testing. By using the same code base, it is easier to get a good correlation between the results, since any difference due to algorithm implementation can be ruled out. The algorithms include a static test where differential nonlinearity (DNL), integral nonlinearity (INL), offset and gain error are calculated using a sine-wave based histogram approach. A dynamic test with an FFT algorithm, that for example calculates signal-to-noise ratio (SNR) and total harmonic distortion (THD), is also included. All algorithms are based on the IEEE Standard for Terminology and Test Meth- ods for Analog-to-Digital Converters (IEEE Std 1241). To generate a sine-wave test signal it is attempted to use a delta-sigma DAC implemented in the FPGA fabric.
Synthesizing the C code algorithms and running them on the FPGA proved successful. For the static test there was a perfect match of the results to 10 decimal places, between the algorithms running on a computer and on the FPGA, and for the dynamic test there was a match to two decimal places. Using a delta-sigma DAC to generate a test sine-wave did not prove feasible in this case. Assuming a brick-wall bandpass filter the performance of the delta-sigma DAC is estimated to an SNR of 53dB, and this signal is not pure enough to test the test case ADC with a specified SNR of 60dB.
Place, publisher, year, edition, pages
2014. , 66 p.
FPGA, BIST, ADC, dynamic test, static test, linearity, DNL, INL, offset, gain error, FFT, SNR, THD, delta-sigma, sigma-delta, DAC, high-level synthesis, HLS, IEEE Standard 1241
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-106602ISRN: LiTH-ISY-EX--14/4747--SEOAI: oai:DiVA.org:liu-106602DiVA: diva2:716974
Subject / course
Wikner, J Jacob, Dr.