Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
2014 (English)In: Mixed Design of Integrated Circuits and Systems (MIXDES), 2014 Proceedings of the 21st International Conference, Poland, 2014, 185-188 p.Conference paper (Refereed)
The paper presents the design of a single-ended amplifier in 1.8~V, 180 nm CMOS process forbuffering the reference voltage in a 10-bit 1-MS/s successive-approximation register (SAR) ADC. The design addresses the comprehensive requirements on the buffersuch as settling time, PSRR, noise, stability, capacitive load variation and power-down features which would be required in a SAR ADC for embedded applications. The buffer is optimized for current consumption and area. Transistor schematic level simulation achieves worst-case settling time of 19.3~ns andcurrent consumption of 66~$\mu$A while occupying an area of (19.2~$\mu$m $\times$ 19.2~$\mu$m).
Place, publisher, year, edition, pages
Poland, 2014. 185-188 p.
SAR ADC, Reference voltage buffer, DAC
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-106913DOI: 10.1109/MIXDES.2014.6872182ISI: 000345852100036ScopusID: 2-s2.0-84906699621ISBN: 978-83-63578-04-6OAI: oai:DiVA.org:liu-106913DiVA: diva2:719525
21st International Conference, Mixed Design of Integrated Circuits and Systems (MIXDES 2014), June 19-21, 2014, Lublin, Poland