A Study of clocking techniques to reduce Simultaneous Switching Noise (SSN) in on-chip application
Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
Simultaneous Switching Noise (SSN) is one of the major problems in today highspeed circuits. Power-Ground voltage fluctuation is significantly increasing due to L ∗ (di/dt)) noise known as Power-Ground bounce and can be one major noise source in modern and mixed-signal circuit design.
In this thesis first SSN and its sources are studied followed by some theoretical analysis, then we present some clock shapes that cause in SSN reduction.
In this thesis, we investigate different clocking techniques in order to reduce SSN. The effect of rise/fall time variation, applying sinusoidal, multi-segment and harmonic suppressed clocks have been investigated and verified by proper circuit simulations.
Multi-segment clock shape and harmonic suppression clock shape produce less noise in comparison to conventional clock, so using them as clock of the whole system can be act as noise reduction technique.
Place, publisher, year, edition, pages
2011. , 47 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-107384ISRN: LiTH-ISY-EX--11/4460--SEOAI: oai:DiVA.org:liu-107384DiVA: diva2:723820
Subject / course