liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
A Study of clocking techniques to reduce Simultaneous Switching Noise (SSN) in on-chip application
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
Abstract [en]

Simultaneous Switching Noise (SSN) is one of the major problems in today highspeed circuits. Power-Ground voltage fluctuation is significantly increasing due to L ∗ (di/dt)) noise known as Power-Ground bounce and can be one major noise source in modern and mixed-signal circuit design.

In this thesis first SSN and its sources are studied followed by some theoretical analysis, then we present some clock shapes that cause in SSN reduction.

In this thesis, we investigate different clocking techniques in order to reduce SSN. The effect of rise/fall time variation, applying sinusoidal, multi-segment and harmonic suppressed clocks have been investigated and verified by proper circuit simulations.

Multi-segment clock shape and harmonic suppression clock shape produce less noise in comparison to conventional clock, so using them as clock of the whole system can be act as noise reduction technique.

Place, publisher, year, edition, pages
2011. , 47 p.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-107384ISRN: LiTH-ISY-EX--11/4460--SEOAI: oai:DiVA.org:liu-107384DiVA: diva2:723820
Subject / course
Electronic Devices
Available from: 2014-06-16 Created: 2014-06-11 Last updated: 2014-06-16Bibliographically approved

Open Access in DiVA

fulltext(2457 kB)153 downloads
File information
File name FULLTEXT01.pdfFile size 2457 kBChecksum SHA-512
ffa610cd7c11afbaae7e44bd66f1e7d0516118d65604c70e8ea57ea9d02ece06129f6b7efe161af909e8ac52d6761e8604a4c65080eb398760f105fb1b3c9301
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Kashfolayat, Sahar
By organisation
Electronic DevicesThe Institute of Technology
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 153 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 94 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf