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ePUMA: A unique memory access based parallel DSP processor for SDR and CR
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2013 (English)In: Global Conference on Signal and Information Processing (GlobalSIP), 2013 IEEE, IEEE , 2013, 1234-1237 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents ePUMA, a master-slave heterogeneous DSP processor for communications and multimedia. We introduce the ePUMA VPE, a vector processing slave-core designed for heavy DSP workloads and demonstrate how its features can used to implement DSP kernels that efficiently overlap computing, data access and control to achieve maximum datapath utilization. The efficiency is evaluated by implementing a basic set of kernels commonly used in SDR. The experiments show that all kernels asymptotically reach above 90% effective datapath utilization. while many approach 100%, thus the design effectively overlaps computing, data access and control. Compared to popular VLIW solutions, the need for a large register file with many ports is eliminated, thus saving power and chip area. When compared to a commercial VLIW solution, our solution also achieves code size reductions of up to 30 times and a significantly simplified kernel implementation.

Place, publisher, year, edition, pages
IEEE , 2013. 1234-1237 p.
Keyword [en]
digital signal processing chips; parallel processing; CR; DSP kernels; SDR; data access; ePUMA VPE; master-slave heterogeneous DSP processor; maximum datapath utilization; memory access based parallel DSP processor; vector processing element; vector processing slave-core; Assembly; Computer architecture; Digital signal processing; Kernel;Registers; VLIW; Vectors; DSP; SDR; VPE; ePUMA
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-109322DOI: 10.1109/GlobalSIP.2013.6737131ISBN: 978-147990248-4 (print)OAI: oai:DiVA.org:liu-109322DiVA: diva2:737549
Conference
1st IEEE Global Conference on Signal and Information Processing (GlobalSIP 2013), 3-5 December 2013, Austin, TX, USA
Available from: 2014-08-13 Created: 2014-08-13 Last updated: 2014-11-28Bibliographically approved

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Karlsson, AndréasSohl, JoarWang, JianLiu, Dake

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