A Digital-RF Converter Architecture for IQ Modulator with Discrete-Time Low Resolution Quadrature LO
2013 (English)In: 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), IEEE , 2013, 641-644 p.Conference paper (Refereed)
A digital-to-RF converter (DRFC) architecture for IQ modulator is proposed in this paper. The digital-RF converter utilizes the mixer DAC concept but a discrete-time oscillatory signal is applied to the digital-RF converter instead of a conventional continuous-time LO. The architecture utilizes a low pass Sigma Delta modulator and a semi-digital FIR filter. The digital Sigma Delta modulator provides a single-bit data stream to a current-mode SDFIR filter in each branch of the IQ modulator. The filter taps are realized as weighted one-bit DACs and the filter response attenuates the out-of-band shaped quantization noise generated by the Sigma Delta modulator. To find the semi-digital FIR filter response, an optimization problem is formulated. The magnitude metrics in out-of-band is set as optimization constraint and the total number of unit elements required for the DAC/mixer is set as the objective function. The proposed architecture and the design technique is described in system level and simulation results are presented to support the feasibility of the solution.
Place, publisher, year, edition, pages
IEEE , 2013. 641-644 p.
Digital-to-analog converter; Mixer DAC; RFDAC; semi-digital FIR filter; SDFIR filter; IQ modulator; digital-RF converters
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-109895DOI: 10.1109/ICECS.2013.6815496ISI: 000339725900166ISBN: 978-1-4799-2452-3OAI: oai:DiVA.org:liu-109895DiVA: diva2:741526
2013 IEEE International Conference on Electronics, Circuits, and Systems, 8-11 December 2013, Abu Dhabi