A Case Study of Code Generator Generation for Embedded SIMD Computers
1996 (English)Conference paper (Refereed)
Can today's most advanced compiler generation systems handle specialized parallel processor architectures? To answer this question, a compiler targeting the embedded RVIP SIMD architecture was generated, using a combination of the DML-P front-end generator and the BEG back-end generator from the CoSy compiler generation toolset. A number of difficulties were encountered when specifying the code generator, for example disability to denote arbitrary register sequences in BEG specifications. However, the end result was positive and a number of lessons were learned on how to improve and generalize the code generation framework. An industrial-strength radar image filtering application was compiled with the generated compiler, giving a benchmarked performance of 2.8 times slower compared to the the same application implemented in micro-code like assembly. Despite the slow-down, industry considered this to be much better than expected.
Place, publisher, year, edition, pages
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-110150OAI: oai:DiVA.org:liu-110150DiVA: diva2:743177
6th Workshop on Compilers for Parallel Computers, Aachen, Germany, Dec 11-13