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A Case Study of Code Generator Generation for Embedded SIMD Computers
Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, PELAB - Programming Environment Laboratory. Linköping University, The Institute of Technology.ORCID iD: 0000-0002-3435-4996
1996 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Can today's most advanced compiler generation systems handle specialized parallel processor architectures? To answer this question, a compiler targeting the embedded RVIP SIMD architecture was generated, using a combination of the DML-P front-end generator and the BEG back-end generator from the CoSy compiler generation toolset. A number of difficulties were encountered when specifying the code generator, for example disability to denote arbitrary register sequences in BEG specifications. However, the end result was positive and a number of lessons were learned on how to improve and generalize the code generation framework. An industrial-strength radar image filtering application was compiled with the generated compiler, giving a benchmarked performance of 2.8 times slower compared to the the same application implemented in micro-code like assembly. Despite the slow-down, industry considered this to be much better than expected.

Place, publisher, year, edition, pages
1996.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-110150OAI: oai:DiVA.org:liu-110150DiVA: diva2:743177
Conference
6th Workshop on Compilers for Parallel Computers, Aachen, Germany, Dec 11-13
Available from: 2014-09-03 Created: 2014-09-03 Last updated: 2014-10-02

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Fritzson, Peter

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