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Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 62, no 1, 273-282 p.Article in journal (Refereed) Published
Abstract [en]

Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.

Place, publisher, year, edition, pages
IEEE , 2014. Vol. 62, no 1, 273-282 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-110393DOI: 10.1109/TCSI.2014.2347231ISI: 000347706500029OAI: oai:DiVA.org:liu-110393DiVA: diva2:745290
Available from: 2014-09-10 Created: 2014-09-10 Last updated: 2017-12-05Bibliographically approved

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Ojani, AminMesgarzadeh, BehzadAlvandpour, Atila

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