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A Unified WCET Analysis Framework for Multicore Platforms
National University of Singapore, Singapore.
National University of Singapore, Singapore.
National University of Singapore, Singapore.
Technical University of Dortmund, Germany.
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2014 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 13, no 124Article in journal (Refereed) Published
Abstract [en]

With the advent of multicore architectures, worst-case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2014. Vol. 13, no 124
Keyword [en]
Design; Performance; Verification; WCET; shared cache; shared bus; multicore
National Category
Computer and Information Science
URN: urn:nbn:se:liu:diva-111298DOI: 10.1145/2584654ISI: 000341390100007OAI: diva2:755287

Funding Agencies|A*STAR public sector funding project from Singapore [1121202007, R252-000-476-305]; ArtistDesign Network of Excellence (the European Community) [216008]; Deutsche Forschungsgemeinschaft (DFG) [FA 1017/1-1]

Available from: 2014-10-14 Created: 2014-10-14 Last updated: 2014-10-22Bibliographically approved

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Chattopadhyay, Sudipta
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