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Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.ORCID iD: 0000-0003-3470-3911
2014 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, 641-645 p.Article in journal (Refereed) Published
Abstract [en]

In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2014. Vol. 61, no 9, 641-645 p.
Keyword [en]
Delta-sigma (Delta Sigma); error-feedback multibit modulator; oversampling digital-to-analog converter
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-111264DOI: 10.1109/TCSII.2014.2331105ISI: 000341985600001OAI: oai:DiVA.org:liu-111264DiVA: diva2:755591
Available from: 2014-10-15 Created: 2014-10-14 Last updated: 2017-12-05Bibliographically approved
In thesis
1. Complexity and Power Reduction in Digital Delta-Sigma Modulators
Open this publication in new window or tab >>Complexity and Power Reduction in Digital Delta-Sigma Modulators
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ΔΣ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation.

In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.

Further on, it is described that the architectural properties of a unit element-based DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.

A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.

All of the designs are subjected to rigorous analysis and are described mathematically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. 70 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1640
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112897 (URN)10.3384/diss.diva-112897 (DOI)978-91-7519-154-6 (ISBN)
Public defence
2015-01-29, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2014-12-19 Created: 2014-12-19 Last updated: 2015-03-11Bibliographically approved

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Afzal, NadeemWikner, JacobGustafsson, Oscar

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