Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
2014 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, Vol. 61, no 9, 641-645 p.Article in journal (Refereed) Published
In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2014. Vol. 61, no 9, 641-645 p.
Delta-sigma (Delta Sigma); error-feedback multibit modulator; oversampling digital-to-analog converter
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-111264DOI: 10.1109/TCSII.2014.2331105ISI: 000341985600001OAI: oai:DiVA.org:liu-111264DiVA: diva2:755591