Improved GaN-on-SiC transistor thermal resistance by systematic nucleation layer growth optimization
2013 (English)In: Compound Semiconductor Integrated Circuit Symposium (CSICS), 2013 IEEE, IEEE , 2013, 1-4 p.Conference paper (Refereed)
Impressive power densities have been demonstrated for GaN-on-SiC based high-power high-frequency transistors, although further gains can be achieved by further minimizing the device thermal resistance. A significant 10-30% contribution to the total device thermal resistance originates from the high defect density AlN nucleation layer at the GaN/SiC interface. This thermal resistance contribution was successfully reduced by performing systematic growth optimization, investigating growth parameters including: Substrate pretreatment temperature, growth temperature and deposition time. Interfacial thermal resistance, characterized by time resolved Raman thermography measurements AlGaN/GaN HEMT structures, were minimized by using a substrate pretreatment and growth temperature of 1200 °C. Reducing the AlN thickness from 105 nm (3.3×10-8W/m2K) to 35 nm (3.3×10-8 W/m2K), led to a ~2.5× interfacial thermal resistance reduction and the lowest value reported for a standard AlGaN/GaN HEMT structure.
Place, publisher, year, edition, pages
IEEE , 2013. 1-4 p.
Gallium nitride, HEMTs, optical microscopy, Raman scattering, semiconductor growth, temperature measurement, thermal analysis, thermal resistance
IdentifiersURN: urn:nbn:se:liu:diva-111501DOI: 10.1109/CSICS.2013.6659233ISBN: 978-147990583-6OAI: oai:DiVA.org:liu-111501DiVA: diva2:756850
35th IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS 2013), Monterey, CA, USA, 13-16 October 2013