On-chip Pipelined Parallel Mergesort on the Intel Single-Chip Cloud Computer
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
With the advent of mass-market consumer multicore processors, the growing trend in the consumer off-the-shelf general purpose processor industry has moved away from increasing clock frequency as the classical approach for achieving higher performance. This is commonly attributed to the well-known problems of power consumption and heat dissipation with high frequencies and voltage.
This paradigm shift has prompted research into a relatively new field of "many-core" processors, such as the Intel Single-chip Cloud Computer. The SCC is a concept vehicle, an experimental homogenous architecture employing 48 IA32 cores interconnected by a high-speed communication network.
As similar multiprocessor systems, such as the Cell Broadband Engine, demonstrate a significantly higher aggregate bandwidth in the interconnect network than in memory, we examine the viability of a pipelined approach to sorting on the Intel SCC. By tailoring an algorithm to the architecture, we investigate whether this is also the case with the SCC and whether employing a pipelining technique alleviates the classical memory bottleneck problem or provides any performance benefits.
For this purpose, we employ and combine different classic algorithms, most significantly, parallel mergesort and samplesort.
Place, publisher, year, edition, pages
2014. , 88 p.
intel, scc, many-core, pipelined, sorting, mergesort, algorithms
Computer Engineering Computer Science
IdentifiersURN: urn:nbn:se:liu:diva-111513ISRN: LIU-IDA/LITH-EX-A--14/012--SEOAI: oai:DiVA.org:liu-111513DiVA: diva2:757030
Subject / course
Master's programme in Computer Science
2014-02-21, Donald Knuth, B-huset, Linköping, 10:00 (English)
Kessler, ChristophMelot, Nicolas, Ph.D. candidate
Kessler, Christoph, Prof. Dr.