A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
2015 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, 28-38 p.Article in journal (Refereed) Published
This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.
Place, publisher, year, edition, pages
Elsevier, 2015. Vol. 50, 28-38 p.
IdentifiersURN: urn:nbn:se:liu:diva-111957DOI: 10.1016/j.vlsi.2015.01.002ISI: 000357054300003OAI: oai:DiVA.org:liu-111957DiVA: diva2:762360