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Building Blocks for Low-Voltage Analog-to-Digital Interfaces
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.

To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ while consuming 6.8 mW.

Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain  frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.

Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium resolution. The generation and buffering of reference voltages is often not the focus of published works. For high-speed SAR ADCs, due to the sequential nature of the successive approximation algorithm, a high-frequency clock for the SAR logic is needed. As the digital-to-analog converter (DAC) output voltage needs to settle to the desired accuracy within half clock cycle period of the system clock, a speed limitation occurs due to imprecise DAC settling. The situation is exacerbated by parasitic inductance of bondwires and printed circuit board (PCB) traces especially when the reference voltages are supplied off-chip. In this thesis, a power efficient reference voltage buffer with small area has been implemented in 180 nm CMOS for a 10-bit 1 MS/s SAR ADC which is intended to be used in a fingerprint sensor. Since the reference voltage buffer is part of an industrial SoC, critical performance specifications such as fast settling, high power supply rejection ratio (PSRR), and low noise have to be satisfied under mismatch conditions and over the entire range of process, supply voltage and temperature (PVT) corners. A single-ended, current-mirror amplifier with cascodes has been designed to buffer the reference voltage. Performance of the buffer has been verified by exhaustive simulations on the post-layout extracted netlist.

Finally, we describe the design of a 10-bit 50 MS/s SAR ADC in 65 nmCMOS with a high-speed, on-chip reference voltage buffer. In a SAR ADC, the capacitive array DAC is the most area-intensive block. Also a binary-weighted capacitor array has a large spread of capacitor values for moderate and high resolutions which leads to increased power consumption. In this work, a split binary-weighted capacitive array DAC has been used to reduce area and power consumption. The proposed ADC has bootstrapped sampling switches which meet 10-bit linearity over all PVT corners and a two-stage dynamic comparator. The important design parameters of the reference voltage buffer are derived in the context of the SAR ADC. The impact of the buffer on the ADC performance is illustrated by simulations using bondwire parasitics. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner, and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. , 44 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1666
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-111958DOI: 10.3384/lic.diva-111958ISBN: 978-91-7519-302-1 (print)OAI: oai:DiVA.org:liu-111958DiVA: diva2:762365
Presentation
2014-09-05, Visionen, Hus B, Campus Valla, Linköpings universitet, 10:15 (English)
Opponent
Supervisors
Available from: 2014-11-11 Created: 2014-11-11 Last updated: 2014-11-11Bibliographically approved
List of papers
1. An Analog Receiver Front-End for Capacitive Body-Coupled Communication
Open this publication in new window or tab >>An Analog Receiver Front-End for Capacitive Body-Coupled Communication
2012 (English)In: NORCHIP, 2012, IEEE , 2012, 1-4 p.Conference paper, Poster (with or without abstract) (Other academic)
Abstract [en]

This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

Place, publisher, year, edition, pages
IEEE, 2012
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-84302 (URN)10.1109/NORCHP.2012.6403137 (DOI)978-1-4673-2222-5 (ISBN)978-1-4673-2221-8 (ISBN)
Conference
30th Norchip Conference 2012, The Nordic Microelectronics event, 12-13 November 2012, Copenhagen, Denmark
Available from: 2012-10-04 Created: 2012-10-04 Last updated: 2015-11-26Bibliographically approved
2. Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
Open this publication in new window or tab >>Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
2013 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2013, IEEE conference proceedings, 2013, 381-384 p.Conference paper, Oral presentation only (Refereed)
Abstract [en]

This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2013
Series
International Symposium on Circuits and Systems (ISCAS), ISSN 0271-4302 ; 2013
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-87996 (URN)10.1109/ISCAS.2013.6571860 (DOI)000332006800094 ()978-1-4673-5760-9 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China
Available from: 2013-01-28 Created: 2013-01-28 Last updated: 2015-11-18
3. Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
Open this publication in new window or tab >>Design of a Reference Voltage Buffer for a 10-bit 1-MS/s SAR ADC
2014 (English)In: Mixed Design of Integrated Circuits and Systems (MIXDES), 2014 Proceedings of the 21st International Conference, Poland, 2014, 185-188 p.Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents the design of a single-ended amplifier in 1.8~V, 180 nm CMOS process forbuffering the reference voltage in a 10-bit 1-MS/s successive-approximation register (SAR) ADC. The design addresses the comprehensive requirements on the buffersuch as settling time, PSRR, noise, stability, capacitive load variation and power-down features which would be required in a SAR ADC for embedded applications. The buffer is optimized for current consumption and area. Transistor schematic level simulation  achieves worst-case settling time of 19.3~ns andcurrent consumption of 66~$\mu$A while occupying an area of (19.2~$\mu$m $\times$ 19.2~$\mu$m).

Place, publisher, year, edition, pages
Poland: , 2014
Keyword
SAR ADC, Reference voltage buffer, DAC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-106913 (URN)10.1109/MIXDES.2014.6872182 (DOI)000345852100036 ()2-s2.0-84906699621 (Scopus ID)978-83-63578-04-6 (ISBN)
Conference
21st International Conference, Mixed Design of Integrated Circuits and Systems (MIXDES 2014), June 19-21, 2014, Lublin, Poland
Available from: 2014-05-26 Created: 2014-05-26 Last updated: 2015-11-18
4. A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
Open this publication in new window or tab >>A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with On-Chip Reference Voltage Buffer
2015 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, 28-38 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an onchip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversionstep while occupying a core area of 0.055 mm2.

Place, publisher, year, edition, pages
Elsevier, 2015
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-111957 (URN)10.1016/j.vlsi.2015.01.002 (DOI)000357054300003 ()
Available from: 2014-11-11 Created: 2014-11-11 Last updated: 2017-12-05Bibliographically approved

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Harikumar, Prakash

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