Power-efficient time-to-digital converter for all-digital frequency locked loops
2015 (English)In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), Institute of Electrical and Electronics Engineers (IEEE), 2015, 300-303 p.Conference paper (Refereed)
An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This architecture allows for an area efficient and power efficient implementation. Thetarget application for the TDC is an all-digital frequency-locked loop which is alsooverviewed in the paper. A prototype chip has been implemented in a 65 nm CMOSprocess with an active core area of 75μmˆ120μm. The time resolution is 5.7 ps with apower consumption of 1.85 mW measured at 50 MHz sampling frequency.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015. 300-303 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-112589DOI: 10.1109/ECCTD.2015.7300008ISI: 000380498200010ISBN: 978-1-4799-9877-7OAI: oai:DiVA.org:liu-112589DiVA: diva2:768523
European Conference on Circuit Theory and Design (ECCTD)