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Selected Applications of Switched Capacitor Circuits: RF N-Path Filters and ΣΔ Modulators
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Electronic circuits based on switches and capacitors have been used in various applications for several decades. The common switched capacitor (SC) circuits have made their career primarily in analog filters and data converters due to high immunity to capacitance mismatch in integrated circuit (IC) technologies. Recently, also in other fields, circuits using switches and capacitors appeared very attractive. In particular, tunable sampling receiver frontends and N-path RF filters have proven very useful; the latter as a tunable integrated replacement for surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters. In this work addressed are applications of SC technique in ΣΔ modulators and RF bandpass filters.

In a typical receiver frontend the SAW or BAW filters are placed after the antenna to suppress the out-of-band interferers (OBI) that can have power levels as high as 0 dBm. These filters by their nature are neither tunable over frequency nor programmable for different bandwidths. Recently, several SAW-less receivers have been proposed based on the idea of N-path filters that are built with switches and capacitors and driven by N-phase non-overlapping clock. N-path filters make use of baseband impedance upconversion and are tunable with clock frequency. However, with capacitors at baseband, the resulting second order RF filter can only provide a limited blocker rejection.

The first contribution of this work is a tunable zero-IF receiver font-end which employs two 4-path bandpass filters in cascade that operate over the frequency range of (0.5-3) GHz. Each filter section is composed of low noise trans-conductance amplifier (LNTA) and a 4-path structure based on switches and capacitors. The second stage also serves as a downconversion mixer in this architecture. In order to avoid loading effects and thereby guarantee high blocker rejection, a voltage buffer is placed between the stages. The 4-path filter gain is estimated by linear periodically varying (LPV) model which accurately captures the RF filter gain in the presence of parasitic capacitance of the amplifier and the switches. The model is also suited to account for the possible clock phase mismatch effects. Fabricated in CMOS 65 nm technology the measured frontend has achieved out-of-band IIP3 and out-of-band P1dB of +15 dBm and +5 dBm respectively. The NF varies from 3.2 to 5.3 dB at 0.5 GHz to 3 GHz. A blocker rejection of 60 dB is achieved at 0.5 GHz which reduces gradually with frequency to 38 dB at 3 GHz.

Another technique suitable for high rejection filtering at RF is based on subtraction of two bandpass filter responses with slightly different center frequencies. Combining the frequency responses in this way also results in better shaping of the filter passband. The necessary offset frequency can be obtained with one clock frequency and quadrature coupled virtual LC tanks at baseband using gm − C cells. In this work the N-path filter is adopted to serve in a low-IF receiver frontend where the effect of 1/f noise of gm cells can be mitigated. For this purpose, the offset frequencies of both filter branches are chosen to be either positive or negative against the carrier. In this setup the filter is also used as a quadrature downconversion mixer. Importantly, some image rejection is already achieved at RF and it is upto 15 dB after downconversion to IF, relaxing thereby the demands for the ultimate image rejection. Simulated in 65 nm CMOS technology the frontend achieves out-of-band IIP3 of 8 dBm, NF of less than 6 dB while image rejection (IR) at RF and IF is 4.8 dB and 15 dB, respectively.

Another contribution of this work is the design of passive SC ΣΔ modulators for low frequency applications. A low frequency ultra-low-power passive modulator was designed in 65 nm CMOS technology and by exploring the design space it was optimized for signal-to-noise and distortion ratio (SNDR). Using a second order SC filter the modulator demonstrated in measurements SNDR = 67 dB and a figure of merit (FOM) of 0.296 pJ/step, which in a comparative design study was superior to its counterparts, semi-passive and active SC ΣΔ modulators.

Furthermore the analysis and design procedures of passive SC ΣΔ modulator are revisited. Presented is the optimization of the noise transfer function (NTF) of second order passive SC modulator in the design space defined by the filter capacitor ratios and the feedback coefficients. Included is a detailed analysis of the thermal noise of the loop filter and the quantizer. Quantization noise, and other parasitic effects are thoroughly analyzed as well. After the optimization, high level simulations show good compliance with the measurement results. Peak SNDR of 73.7/68.4 dB, DR of 73.4/70.7 dB and MSA of -6.6/-4.3 dBFS is measured in 65 nm CMOS process for the sampling frequency of 500 kHz/250 kHz, respectively, while the attained minimum FOM is 0.17 pJ/step.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. , 63 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1627
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-112882ISBN: 978-91-7519-210-9 (print)OAI: oai:DiVA.org:liu-112882DiVA: diva2:773313
Public defence
2015-01-14, Signalen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2016-01-18Bibliographically approved
List of papers
1. Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
Open this publication in new window or tab >>Two Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
2015 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 62, no 5, 421-425 p.Article in journal (Refereed) Published
Abstract [en]

In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. The effect of thermal noise folding on the circuit noise figure, as well as clock phase mismatch on filter gain are also discussed. As a proof of concept, a chip design of a tunable radio-frequency front end using 65-nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB, out of band IIP3 > +17 dBm and blocker P1 dB > +5 dBm over frequency range of 0.5-3 GHz.

Keyword
SAW-less receiver, N-path filter, wideband selective RF front-end
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112879 (URN)10.1109/TCSII.2014.2385213 (DOI)000353636400001 ()
Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2017-12-05Bibliographically approved
2. Tunable Selective Receiver Front-End with Impedance Transformation Filtering
Open this publication in new window or tab >>Tunable Selective Receiver Front-End with Impedance Transformation Filtering
2016 (English)In: International journal of circuit theory and applications, ISSN 0098-9886, E-ISSN 1097-007X, Vol. 44, no 5, 1071-1093 p.Article in journal (Refereed) Published
Abstract [en]

A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is proposed in this paper. To achieve blocker rejection comparable to SAW filters, we use a two stage architecture based on a low noise trans-conductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying (LPV) model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate “back folding” by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept a chip design of a tunable RF front-end using 65 nm CMOS technology is presented. In measurements the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2-5.2 dB,out of bandIIP3 > +17 dBm and blocker P1dB > +5 dBm over frequency range of 0.5—3 GHz.

Place, publisher, year, edition, pages
John Wiley & Sons, 2016
Keyword
SAW-less receiver; N-path filter; wideband selective RF front-end
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:liu:diva-122701 (URN)10.1002/cta.2125 (DOI)000376206000009 ()
Available from: 2015-11-16 Created: 2015-11-16 Last updated: 2017-12-01Bibliographically approved
3. Blocker and Image Reject Low-IF Frontend
Open this publication in new window or tab >>Blocker and Image Reject Low-IF Frontend
2013 (English)In: European Conference on Circuit Theory and Design (ECCTD), 2013, IEEE , 2013, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a design of a low-IF receiver frontend using a selective N-path filter which serves blocker rejection, image rejection, and downconversion. The filter makes use of quadrature impedance upconversion technique using multiphase clocking and can be programmed by baseband capacitance and gm-cell transconductance values to meet the low-IF criterion in various cases. Presented is both a mathematical model of the filter and circuit simulation results including parasitic effects. Image rejection of 14 dB at IF that is provided by the filter mitigates the demands for the ultimate image rejection by the IQ mode. The blocker rejection at IF is larger than 50 dB. Designed in in 65 nm CMOS the low-IF receiver frontend with a modified N-path filter in simulations achieves NF <; 6 dB and OOB IIP3 > +8 dBm in 0.5-1 GHz band.

Place, publisher, year, edition, pages
IEEE, 2013
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-97269 (URN)10.1109/ECCTD.2013.6662258 (DOI)978-300043785-4 (ISBN)
Conference
European Conference on Circuit Theory and Design (ECCTD), September 8-12, Dresden, Germany
Available from: 2013-09-05 Created: 2013-09-05 Last updated: 2014-12-18Bibliographically approved
4. Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
Open this publication in new window or tab >>Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 2, 358-370 p.Article in journal (Refereed) Published
Abstract [en]

A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-102756 (URN)10.1109/TCSI.2013.2278346 (DOI)000331191800004 ()
Available from: 2013-12-20 Created: 2013-12-20 Last updated: 2017-12-06Bibliographically approved
5. Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study
Open this publication in new window or tab >>Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study
2015 (English)In: IEEE Journal of Emerging and Selected Topics in Power Electronics, ISSN 2168-6777, E-ISSN 2168-6785, Vol. 5, no 4, 624-637 p.Article in journal (Refereed) Published
Abstract [en]

In this paper we study passive switch-capacitor sigma-delta (ΣΔ) modulators suitable for low power applications. Using a one-bit quantizer as the only active block those modulators save power and achieve high linearity. However, their order is largely limited since the passive loop filter presents a significant attenuation to the signal. Typically with a secondorder filter the modulator can achieve a satisfactory signal-toquantization-noise ratio (SQNR) by using a large enough oversampling (OSR) that also creates a tradeoff with the power consumption. A passive ΣΔ modulator when modeled as a linear system requires extraction of the equivalent loop gain. It is shown that for this purpose the quantization and thermal noise should be considered jointly. The paper presents optimization of the modulator in the design space defined by the filter capacitor ratios and the feedback coefficients. Included is a detailedanalysis of the thermal noise, quantization noise, and other parasitic effects. The discussion is supported by 65 nm CMOS chip measurements showing power consumption < 0.62μW, SNDR = 73 dB, and energy efficiency < 0.17 pJ/step.

Place, publisher, year, edition, pages
IEEE Press, 2015
Keyword
Passive sigma-delta modulator, passive SC filter, ADC, CMOS, thermal noise in SC circuit, equivalent quantizer gain
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112881 (URN)10.1109/JETCAS.2015.2502169 (DOI)000367302600013 ()
Note

Vid tiden för disputation förelåg publikationen endast som manuskript

Available from: 2014-12-18 Created: 2014-12-18 Last updated: 2017-12-05

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