Power efficient arrangement of oversampling sigma-delta DAC
2012 (English)In: NORCHIP, 2012, IEEE , 2012, 1-4 p.Conference paper (Refereed)
A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.
Place, publisher, year, edition, pages
IEEE , 2012. 1-4 p.
digital-analogue conversion;sigma-delta modulation;DSDM;buss-split design;digital sigma-delta modulator;digital-to-analog conversion blocks;hardware efficient arrangement;oversampling sigma-delta DAC;power efficient arrangement;Complexity theory;Hardware;Modulation;Quantization;Sigma delta modulation;Signal to noise ratio;DAC complexity;Digital sigma-delta modulator;bit-split;composite architecture;modulator’s complexity;noise shaping
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-112892DOI: 10.1109/NORCHP.2012.6403119ISBN: 978-1-4673-2221-8 (print)ISBN: 978-1-4673-2222-5 (online)OAI: oai:DiVA.org:liu-112892DiVA: diva2:773513
2012 NORCHIP, November 12-14, Copenhagen, Denmark