Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption
2012 (English)Manuscript (preprint) (Other academic)
The hardware of the multi-bit digital error feedback modulator (EFM) of arbitrary order has recently been reduced by using multiple EFMs in cascade. In this paper, a modified cascading strategy is devised. Parts of the processing of consecutively placed EFM stages are merged such that a significant amount of circuitry is removed in each stage. In the proposed design, the modulated output is represented by a set of encoded signals to be used by the signal processing block placed after the EFM.
To illustrate the savings, a number of configurations of fourth-order EFM designs, composed of two- and three-cascaded stages, have been synthesized in a 65 nm CMOS process technology using conventional and the proposed implementation techniques. Savings of 52.7% and 47%, in terms of area and power consumption, respectively, at an oversampling ratio of 4 could be obtain. The trade-off between sampling frequency and hardware cost is also presented. Due to reduced hardware an increase of up to 600 MHz in the sampling frequency is achieved.
Place, publisher, year, edition, pages
2012. 1-4 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-112896OAI: oai:DiVA.org:liu-112896DiVA: diva2:773519