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Complexity and Power Reduction in Digital Delta-Sigma Modulators
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ΔΣ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation.

In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.

Further on, it is described that the architectural properties of a unit element-based DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.

A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.

All of the designs are subjected to rigorous analysis and are described mathematically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2014. , 70 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1640
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-112897DOI: 10.3384/diss.diva-112897ISBN: 978-91-7519-154-6 (print)OAI: oai:DiVA.org:liu-112897DiVA: diva2:773538
Public defence
2015-01-29, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2014-12-19 Created: 2014-12-19 Last updated: 2015-03-11Bibliographically approved
List of papers
1. Power efficient arrangement of oversampling sigma-delta DAC
Open this publication in new window or tab >>Power efficient arrangement of oversampling sigma-delta DAC
2012 (English)In: NORCHIP, 2012, IEEE , 2012, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.

Place, publisher, year, edition, pages
IEEE, 2012
Keyword
digital-analogue conversion;sigma-delta modulation;DSDM;buss-split design;digital sigma-delta modulator;digital-to-analog conversion blocks;hardware efficient arrangement;oversampling sigma-delta DAC;power efficient arrangement;Complexity theory;Hardware;Modulation;Quantization;Sigma delta modulation;Signal to noise ratio;DAC complexity;Digital sigma-delta modulator;bit-split;composite architecture;modulator’s complexity;noise shaping
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112892 (URN)10.1109/NORCHP.2012.6403119 (DOI)978-1-4673-2221-8 (ISBN)978-1-4673-2222-5 (ISBN)
Conference
2012 NORCHIP, November 12-14, Copenhagen, Denmark
Available from: 2014-12-19 Created: 2014-12-19 Last updated: 2014-12-19Bibliographically approved
2. Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
Open this publication in new window or tab >>Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
2014 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 61, no 9, 641-645 p.Article in journal (Refereed) Published
Abstract [en]

In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keyword
Delta-sigma (Delta Sigma); error-feedback multibit modulator; oversampling digital-to-analog converter
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-111264 (URN)10.1109/TCSII.2014.2331105 (DOI)000341985600001 ()
Available from: 2014-10-15 Created: 2014-10-14 Last updated: 2017-12-05Bibliographically approved
3. On Scaling and Output Cardinality of Multi-Bit Digital Error-Feedback Modulators
Open this publication in new window or tab >>On Scaling and Output Cardinality of Multi-Bit Digital Error-Feedback Modulators
2012 (English)Manuscript (preprint) (Other academic)
Abstract [en]

In order to determine a maximum allowed input scale for the stable operation of higher-order delta-sigma modulators, the designers largely depend on the analytical and numerical analysis. In this brief, the maximum allowed input scale to a multi-bit digital error-feedback  deltasigma modulator of arbitrary order is derived, mathematically. The digital modulator with an arbitrary output word length is stable if its output does not overflow. Thus, to avoid overflow of the modulator output, the relations between the peak values of the involved digital signals are devised. A number of example configurations are presented to illustrate the usefulness of the derivations.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112895 (URN)
Available from: 2014-12-19 Created: 2014-12-19 Last updated: 2015-03-11Bibliographically approved
4. Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption
Open this publication in new window or tab >>Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption
2012 (English)Manuscript (preprint) (Other academic)
Abstract [en]

The hardware of the multi-bit digital error feedback modulator (EFM) of arbitrary order has recently been reduced by using multiple EFMs in cascade. In this paper, a modified cascading strategy is devised. Parts of the processing of consecutively placed EFM stages are merged such that a significant amount of circuitry is removed in each stage. In the proposed design, the modulated output is represented by a set of encoded signals to be used by the signal processing block placed after the EFM.

To illustrate the savings, a number of configurations of fourth-order EFM designs, composed of two- and three-cascaded stages, have been synthesized in a 65 nm CMOS process technology using conventional and the proposed implementation techniques. Savings of 52.7% and 47%, in terms of area and power consumption, respectively, at an oversampling ratio of 4 could be obtain. The trade-off between sampling frequency and hardware cost is also presented. Due to reduced hardware an increase of up to 600 MHz in the sampling frequency is achieved.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112896 (URN)
Available from: 2014-12-19 Created: 2014-12-19 Last updated: 2015-03-11Bibliographically approved

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Afzal, Nadeem

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